Signal wont get out of U-state ????

Discussion in 'VHDL' started by Thor Phersen, Jan 11, 2007.

  1. Thor Phersen

    Thor Phersen Guest

    Im sure this is a stupid question, but I have this signal that just won't
    change. I have two components, linked together in a "master" file. The one
    component has an output, and the other one has an input, assigned to the
    same signal in the "master" design file. This should work fine, right ? I
    have other signals in the design defined in the same way, and they work fine
    !

    I just wonder if any of you have a clue to where I have written something
    wrong ? The system compiles OK in Modelsim, and ISE makes a configuration
    file whithout any complaint. But it does not work. In Modelsim the signal
    appears as U, no matter how many times I assign a value to the signal in the
    VHDL-code. By the way, if it is of any importance, the code consists mainly
    of one-process state mackines.
    Thor Phersen, Jan 11, 2007
    #1
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  2. Thor Phersen wrote:
    > I have two components, linked together in a "master" file. The one
    > component has an output, and the other one has an input, assigned to the
    > same signal in the "master" design file. This should work fine, right ?


    As long as the testbench architecture
    that instances the "master" design file
    also drives the other inputs.

    -- Mike Treseler
    Mike Treseler, Jan 11, 2007
    #2
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