Signal zaehl cannot be synthesized

Discussion in 'VHDL' started by Reload6156, Apr 16, 2007.

  1. Reload6156

    Reload6156

    Joined:
    Apr 16, 2007
    Messages:
    2
    Hi Guys! I've got a problem with my vhdl code. I am very new at programming in this language and for this reason i am not be able to find the mistake. I tried hard without success. Signal zaehl cannot be synthesized, bad synchronous description. I hope somebody can help me. Furthermore, this project must be programmed at school.

    ENTITY zaehler IS
    PORT ( clock, zuendung, automatik : in std_logic;
    katnr, rauf, runter ,sperr_ext :in bit;
    leda, ledb, ledc, ledd, lede, ledf, ledg, dp, ledrauf, ledrunter, ledkatnr, transistor1, transistor2 :eek:ut bit);
    END zaehler ;

    ARCHITECTURE number_one OF zaehler IS

    signal gang : std_logic_vector (2 downto 0);
    signal zaehl : std_logic_vector (5 downto 0);-- badsynchronous description
    signal zaehl_sperr : std_logic_vector (6 downto 0);
    signal zaehl_auto : std_logic_vector (7 downto 0);
    signal gang_alt : std_logic_vector (2 downto 0);

    BEGIN

    PROCESS (clock, zuendung, automatik, katnr, zaehl, zaehl_sperr, zaehl_auto, gang, gang_alt, rauf, runter, sperr_ext)
    BEGIN
    transistor1 <= '0';
    transistor2 <= '1';
    gang <= "001";
    zaehl<= "000000";
    zaehl_sperr <= "1010101";
    zaehl_auto <= "00000000";
     
    Reload6156, Apr 16, 2007
    #1
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  2. Reload6156

    martin.wahlstedt

    Joined:
    Mar 29, 2007
    Messages:
    14
    Remove the signals zaehl, zaehl_sperr, zaehl_auto, gang & gang_alt from the sensitivity list and the problem should be solved. Put only signals that you want your process to trigger on, for instance clock and reset for a synchronous architecture, in the sensitivity list.

    The reason you get the error on 'zaehl' is probably because it is the first one in the list.

    Martin
     
    martin.wahlstedt, Apr 17, 2007
    #2
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