signals VS variables

[omar-saif]

Dear All,

Can i Ask, how signals and variables be represented in a hardware? and what is the difference between them in a clocked process?
another question please, what is the difference between the combinational and sequential process?

thanks in advance.

 

[jeppe]

Hi Omar

Indeed a very important issue trying to understand VHDL.

the free book about VHDL, called Evita (search the net) will answer most of your questions.

Both variables and signal will be translated into logic and F/F's, but if you use variables in a sequential (clock-driven) process will the order of statements matter.
(Could be seen by exampeles of this page: http://jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No9_Shiftreg_Signal_vs_Variable/index.htm)

A combinatorial process should have all input signals (and internal as well) in the sensitivity list, in order to produce combinatorial logic.

A sequential process should normally be trigged by a clock signal and perhaps an asynchronous Clear signal.

Your welcome

 

[KJ]

Dear All,

Can i Ask, how signals and variables be represented in a hardware?

- Variables can be used to help define the logic function of a signal whichin turn get synthesized into some form of 'hardware'
- Variables and signals can each be used to define the logic function inputto a storage element such as a flip flop
- The logic function represented by a signal can be synthesized into hardware in many ways that will be determined by the target hardware. Some of these implementations can be:
* flip flops
* Contents of LUT memory
* Fuse patterns to program or not program

and what is the difference between them in a clocked process?

Variables get updated immediately within the process. This makes them handy to use if you have some complicated logic and don't want to copy/paste itthroughout the process. This is just one example. Signals that get assigned don't get updated until the process suspends so the new assigned value doesn't get used until the next time the process is entered.

another question please, what is the difference between the combinationaland sequential process?

Sequential processes have a clock. The outputs of that process change onlyon the rising (or falling edge if desired) of the clock input. Combinatorial processes potentially can change whenever any of the inputs to the process change.

Kevin Jennings

 

[Paul Uiterlinden]

- Variables can be used to help define the logic function of a signal
which in turn get synthesized into some form of 'hardware' - Variables and
signals can each be used to define the logic function input to a storage
element such as a flip flop
- The logic function represented by a signal can be synthesized into
hardware in many ways that will be determined by the target hardware.
Some of these implementations can be:
* flip flops
* Contents of LUT memory
* Fuse patterns to program or not program

Variables may be synthesized into flip-flops as well. Or latches. It all
depends whether you use the value of the variable from a previous
assignment, e.g. from the previous clock edge.

If used to synthesize flip-flops, variables give the opportunity not only to
use the Q output of a flip-flop in an equation, but also the D input
(although that may lead to long combinatorial paths after synthesis).

process is
variable var_ff: some_type;
begin
wait until clk = '1';

-- using var here is as using the Q output of the var flip-flops.
--
sig1 <= ... var_ff ...;

var_ff := ....; -- New value for var_ff

-- using var here is as using the D input of the var flip-flops.

 

[Andy]

As mentioned in other replies, variables references in clocked
processes can represent either registered or combinatorial logic.

Some organizations discourage use of variables for registered logic.
For such circumstances, it is useful to have a set of coding rules to
allow use of variables for combinatorial logic such that inadvertent
registered logic is not created from references to variables. These
ground rules are similar to those for avoiding latches in
combinatorial processes: use up-front, default assignments to all
variables in the process, before any conditional statements (not
including the "if rising_edge..."). This ensures that no variable,
when referenced later in the process, can contain a value stored in a
previous clock cycle, and thus no register would be inferred.

Because the inference of a register is based on the reference relative
to the most recent assignment, it is possible to have a reference to
the same variable infer registered and combinatorial logic. Consider
the case of a conditional assignment to a variable early in the
process, then later (in the same clock cycle) the variable is
referenced. Whether or not the most recent assignment was in a
previous clock cycle depends upon the conditional logic associated
with the assignment statement. The synthesized hardware will use the
same conditional logic to control a multiplexer that selects either
the combinatorial logic, or the output of a register fed from the same
combinatorial logic (e.g. a bypass multiplexer on the output of the
register).

Andy