signed(12 downto 0) to signed (8 downto 0)

Discussion in 'VHDL' started by kyrpa83, Oct 17, 2007.

  1. kyrpa83

    kyrpa83

    Joined:
    Oct 14, 2007
    Messages:
    3
    Hi!

    In my code i have register which is std_logic_vector(12 downto 0). The register contains signed result which i need to divide by 2 so it can be fidded to std_logic_vector(8 downto 0). I mean that i make the resolution worse and take only the the higher bits of register(and copy the MSB-bit to needed places to fulfill 2┬┤compliment). That kind of code is really easy to make working in simulators but there other thing is to make it work in design vision for making ASIC. Now i am looking for ready-function from libraries to make it happen. Is there a function which skips as many bits as i want and copys sign-bit all necessery places??
    kyrpa83, Oct 17, 2007
    #1
    1. Advertising

  2. kyrpa83

    kyrpa83

    Joined:
    Oct 14, 2007
    Messages:
    3
    ??anyone??
    kyrpa83, Oct 17, 2007
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Brad Smallridge

    std_logic_vector(0 downto 0)

    Brad Smallridge, Nov 12, 2004, in forum: VHDL
    Replies:
    3
    Views:
    8,103
    Michael Riepe
    Nov 12, 2004
  2. Fabian

    downto vs. to

    Fabian, Aug 29, 2007, in forum: VHDL
    Replies:
    4
    Views:
    10,176
    Brad Smallridge
    Aug 31, 2007
  3. pierre0102@gmail.com
    Replies:
    1
    Views:
    1,671
    jeppe
    Nov 18, 2008
  4. hassenman
    Replies:
    3
    Views:
    806
    jeppe
    Mar 14, 2009
  5. zetetic

    "downto" the nitty-gritty

    zetetic, Oct 8, 2005, in forum: Ruby
    Replies:
    3
    Views:
    85
    zetetic
    Oct 9, 2005
Loading...

Share This Page