Signed Division VHDL/FPGA

Discussion in 'VHDL' started by Dan Nilsen, Apr 15, 2005.

  1. Dan Nilsen

    Dan Nilsen Guest

    Hello.

    Does anyone have a synthesizable implementation of 2's complement
    integers for FPGA? The integers in question are of std_logic_vector of
    different number of bits. It does not necessarily need any carry as
    the precision I need isn't very crucial, but the sign is of course
    important.

    Would be good if anyone has any useful source, or if someone can point
    me in the direction of an algorithm for this.

    Cheers,

    Dan
     
    Dan Nilsen, Apr 15, 2005
    #1
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  2. Dan Nilsen

    Praveen Guest

    I suggest you post this question on comp.arch.fpga or comp.dsp group.
    You might get some replies..
     
    Praveen, Apr 15, 2005
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  3. Dan Nilsen

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
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    I have the code available here..
    vhdlguru.blogspot.com/2010/03/vhdl-function-for-division-two-signed.html
    The code is synthesisable.
     
    vipinlal, Mar 17, 2010
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