hi
Can anyone tell me how can i multiply two signed numbers in FPGA.
How the logic is really implemented..
ie., if i multiply two signed numbers are they multiplying the
positive number and the 2's complement (if the number is negative)
directly ..?
Or are they really changing the negative number to positive and do
normal multiplication and appends the sign accordingly..?
And is the positive number, and its 2's complement form same always...?
Multiplication, at it's heart, is nothing more than a sum of all of
the powers in any given number. The same holds for digital
multiplication. Lets first look at unsigned multiplication:
13 * 7 (1101 x 0111)
All that happens is you add up all of the individual powers of two
multiplication, which in binary is a simple bit shift to the left.
0 1 1 1 0 0 0 (8x = 2^3) 1
0 1 1 1 0 0 (4x = 2^2) 1
0 0 0 0 0 (2x = 2^1) 0
+ 0 1 1 1 (1x = 2^0) 1
----------------
0 1 0 1 1 0 1 1 = 91
When multiplying two binary numbers, the number of bits required to
represent the result is always length(a) + length(b).
The rules above still carry through when using two's compliment. Lets
have a look at the same two binary numbers in twos compliment.
7 x -3 (0111 x 1101)
In twos compliment though, you have to remember to extend the sign bit
forward.
0 0 0 0 0 0 0 0 (8x) 0
1 1 1 1 0 1 0 0 (4x) 1
1 1 1 1 1 0 1 0 (2x) 1
+ 1 1 1 1 1 1 0 1 (1x) 1
------------------
1 1 1 1 0 1 0 1 1 = -21.
|
|
-------- We only have an 8 bit result, so bits above bit 7 are
removed.
Fixed point multiplication works in exactly the same way, except that
an m.n x a.b number has a result of length (m + a).(n + b) (the total
number of bits is still the sum of the totals). This means some
additions require a bit shift to the right rather than left (ie. 2^-n)
FPGA's though, often have integrated multipliers and you dont have to
worry about resourcing a large number of adders. The easiest form of
multiplaction in VHDL is:
library ieee.
use ieee.numeric_std.all
.....
.....
.....
signal A, B : unsigned(7 downto 0); --or signed if you wish
signal R : unsigned(15 downto 0); --or signed if you wish, if A
and B are signed
begin
process(clk)
begin
if rising_edge(clk) then
R <= A * B;
end if;
end process;
....
....
Any good synthesiser should assign this to an onboard multiplier (if
it fits - its common for internal multipliers to be 9/18/36 bits or
less). Otherwise it should have knowledge of a multiplier it can build
out of logic.
Also remember though, that multiplying by 2^n is simply a bit shift,
so you dont need to use any logic for that. You simply append 0's or
remove bits.
