signed to unsigned

Discussion in 'VHDL' started by Patrick, Jun 7, 2004.

  1. Patrick

    Patrick Guest

    hello,

    I have to convert a signed signal to an unsigned one... I tried this code ?
    What do you think about ? I just invert the sign bit (bit 13)...

    But i forgot a part of resolution...


    -- Conversion signed -> unsigned
    CONV_US : process (clk_smp,reset)
    begin
    if reset = '1' then I_filter_14_US <= (others => '0');
    Q_filter_14_US <= (others => '0');
    elsif (clk_smp'event and clk_smp='1') then
    I_filter_14_US(13 downto 13) <= not I_filter_14(13 downto 13);
    I_filter_14_US(12 downto 0) <= I_filter_14(12 downto 0);
    Q_filter_14_US(13 downto 13) <= not Q_filter_14(13 downto 13);
    Q_filter_14_US(12 downto 0) <= Q_filter_14(12 downto 0);
    end if;
    end process CONV_US;
     
    Patrick, Jun 7, 2004
    #1
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  2. Patrick wrote:

    > I have to convert a signed signal to an unsigned one...


    For conversions look into the packages, that are provided by your EDA
    tool vendor.
    If you use IEEE.numeric_stad.all, take the following piece of code:

    A_us<=unsigned(B_s);


    Ralf
     
    Ralf Hildebrandt, Jun 7, 2004
    #2
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