Simple counter

Discussion in 'VHDL' started by Golanu`, Apr 5, 2008.

  1. Golanu`

    Golanu`

    Joined:
    Apr 5, 2008
    Messages:
    1
    Hi,

    Because I am a beginner in VHDL, I am constantly having trouble writing code.

    I designed a simple counter and tested it. It works how it should, but when I use this component elsewhere it doesn't work properly, in fact it doesn't work at all.

    This is the way I used the component:

    Code:
    entity Nalfa is
        generic (M:integer:=8);
        port (CLK: in bit;
                Reset: in bit;
                q:out std_logic_vector (M/2-1 downto 0));
    end Nalfa;
    
    
    architecture Behavioral of Nalfa is    
    
    -- unimportant code
    
    component Counter is      
        generic (N:integer);
        port (Clk: in bit;
        reset: in bit;
        ce: in bit;
        load: in bit;
        dir: in bit;
        din:in std_logic_vector(N-1 downto 0);
        count: out std_logic_vector (N-1 downto 0));
    end component;    
    
    signal aux1: std_logic_vector (m/2-1 downto 0 ):=(others=>'0');
    signal count1: std_logic_vector (m/2-1 downto 0 );
    
    begin    
        
        L1: Counter generic  map (N => (M/2))
        port map (Clk,Reset,ce=>'1',load=>Reset,dir=>'1',din=>aux1,count=>count1);     
    
        -- unimportant code
    
        L2: q<=count1;
    
    
    end Behavioral;
    
    Can you please tell me where is the mistake?
    Golanu`, Apr 5, 2008
    #1
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