Simple Memory Read Problem drives me crazy

Discussion in 'VHDL' started by Gerry, Feb 6, 2008.

  1. Gerry

    Gerry Guest

    Hi

    I have a strange bug in my simulation and cant figure out the error.
    I have a simple ram that contains data that should be read as described
    in the following process:

    PROC_ram : process (clk)
    begin
    if (clk'event and clk = '1') then
    -- memory write:
    if (ew_cp0 = '1') then
    ram(conv_integer(unsigned(rw_addr_cp0))) <= data_in_cp0;
    end if;
    if (rst = '0') then -- optional reset
    data_out_cp0 <= (others => '0');
    else
    data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));
    end if;
    end if;
    end process PROC_ram;

    The problem that I have is, that the data is output with a delay of one
    cycle. So when I check the waveforms I see that on a rising edge of the
    clock the address changes to one for instance, but the data is still
    read from memory position zero...

    Anyone an idea what could be wrong here?

    Many thanks!
     
    Gerry, Feb 6, 2008
    #1
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  2. Gerry

    Gerry Guest

    Stupid me, found the error, I should have an asynchronous read....

    Now it looks like this:

    PROC_ram : process (clk)
    begin
    if (clk'event and clk = '1') then
    -- memory write:
    if (ew_cp0 = '1') then
    ram(conv_integer(unsigned(rw_addr_cp0))) <= data_in_cp0;
    end if;
    if (rst = '0') then -- optional reset
    --data_out_cp0 <= (others => '0');
    -- else
    --data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));
    end if;
    end if;
    end process PROC_ram;
    data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));

    In this case the reset port can be omitted, I wanna sythesis this as a
    BRAM on a Xilinx FPGA. Hope that works!
     
    Gerry, Feb 6, 2008
    #2
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  3. Gerry

    Gerry Guest


    > In this case the reset port can be omitted, I wanna sythesis this as a
    > BRAM on a Xilinx FPGA. Hope that works!


    Well unfortuatnely XST tells me that the RAM will be implemented with
    LUTS and that I have to describe it in a way that BRAM can be
    instatiated, so that initial values can be stored in it...

    Anyone who can help me out in this matter?
     
    Gerry, Feb 6, 2008
    #3
  4. Gerry

    Guest

    Hi Gerry,

    Is it possible at all that you can use the Core Generator or simply
    use the BRAM primitives?

    Why exactly are you writing your own RAM module when you want BRAM?

    Cheers.

    On Feb 6, 11:53 pm, Gerry <> wrote:
    > > In this case the reset port can be omitted, I wanna sythesis this as a
    > > BRAM on a Xilinx FPGA. Hope that works!

    >
    > Well unfortuatnely XST tells me that the RAM will be implemented with
    > LUTS and that I have to describe it in a way that BRAM can be
    > instatiated, so that initial values can be stored in it...
    >
    > Anyone who can help me out in this matter?
     
    , Feb 7, 2008
    #4
  5. Gerry

    Gerry Guest

    wrote:
    > Hi Gerry,
    >
    > Is it possible at all that you can use the Core Generator or simply
    > use the BRAM primitives?
    >
    > Why exactly are you writing your own RAM module when you want BRAM?


    Hi

    the problem is, I need an asynchronous RAM for my design. But with BRAM
    you can just implement synchronous RAM. So I would need to know how
    it is possible to initialise distributed RAM (1536 x 32bits) with some
    initial values at startup.

    Any idea if this is possible?
     
    Gerry, Feb 7, 2008
    #5
  6. Gerry

    Andy Guest

    On Feb 7, 5:39 am, Gerry <> wrote:
    > wrote:
    > > Hi Gerry,

    >
    > > Is it possible at all that you can use the Core Generator or simply
    > > use the BRAM primitives?

    >
    > > Why exactly are you writing your own RAM module when you want BRAM?

    >
    > Hi
    >
    > the problem is, I need an asynchronous RAM for my design. But with BRAM
    > you can just implement synchronous RAM. So I would need to know how
    > it is possible to initialise distributed RAM (1536 x 32bits) with some
    > initial values at startup.
    >
    > Any idea if this is possible?


    Depending on your synthesis tool, it may be able to use an initial
    value specified when you declare the array that is used for the
    memory. Check your tool docs.

    Andy
     
    Andy, Feb 7, 2008
    #6
  7. Gerry

    Gerry Guest


    >
    > Depending on your synthesis tool, it may be able to use an initial
    > value specified when you declare the array that is used for the
    > memory. Check your tool docs.


    I used the Xilinx Core generator that generated me a distributed RAM
    and the inital values are provided by a .coe file. I have no included
    a black box for the RAM and the netlist file that was generated I have
    put into my project directory. It is 160kb big, so I hope in this
    netlist are also the inital values specified for the single RAM addresses.

    Hope it works!
     
    Gerry, Feb 7, 2008
    #7
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