Simple question about hexadecimal values

[Massi]

Hi everyone...another newbie question, I'm writing a testbench to send
different address to my unit under test.Each address is compute
starting from a base address (say for example a 32 bit address like
X"10000400"). The piece of code which doesn't work is the following:

for i in 0 to 10 loop
temp := i*4+X"10000400";
address_in_sig <= std_logic_vector(to_unsigned(temp, 32));
-- Send the address to the UUT and verify the output...
end loop;

If I replace X"10000400" with the corresponding unsigned value
everything works, but I wonder which is the right way to code it using
the hexadecima value (which is more readable than 268436480...).
Thanks in advance for your help!

 

[JimLewis]

Massi,

Hi everyone...another newbie question, I'm writing a testbench to send
different address to my unit under test.Each address is compute
starting from a base address (say for example a 32 bit address like
X"10000400"). The piece of code which doesn't work is the following:

for i in 0 to 10 loop
        temp := i*4+X"10000400";
        address_in_sig <= std_logic_vector(to_unsigned(temp, 32));
        -- Send the address to the UUT and verify the output...
end loop;

If I were feeling lazy I would do the following:

use ieee.std_logic_unsigned.all ;

address_in_sig <= i*4 + X"10000400" ;


On the other hand, if you feel the need to avoid this package,
you can do the following:

use ieee.numeric_std.all ;
.. . .
signal address_in_sig_uv : unsigned (31 downto 0) ;
.. . .
address_in_sig_uv <= i*4 + X"10000400" ;

Then do a type conversion in the port map:

U_comp1 : comp1
port map (
address_port => std_logic_vector(address_in_sig_uv),
. . .
) ;


Cheers,
Jim
SynthWorks VHDL Training