simulating 8255

Discussion in 'VHDL' started by Shalini Keshavamurthy, Mar 2, 2008.

  1. hi,
    i want to simulate 8255 using vhdl.
    is there any way to configure a port as an I/P or an O/P based on
    certain conditions in d architecture? how do i go abt it?
     
    Shalini Keshavamurthy, Mar 2, 2008
    #1
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  2. Shalini Keshavamurthy

    Guest

    On Mar 2, 10:56 pm, Shalini Keshavamurthy <>
    wrote:
    > hi,
    > i want to simulate 8255 using vhdl.
    > is there any way to configure a port as an I/P or an O/P based on
    > certain conditions in d architecture? how do i go abt it?



    You'd have to do it using inout ports
     
    , Mar 2, 2008
    #2
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  3. wrote:

    >> i want to simulate 8255 using vhdl.


    FYI been done (a few times) before...

    >> is there any way to configure a port as an I/P or an O/P based on
    >> certain conditions in d architecture? how do i go abt it?

    > You'd have to do it using inout ports


    I'd strongly suggest you don't use inout ports in your 8255 model, but
    rather use input, output and output-enable ports for each 8255 IO port and
    then connect them to bidir (inout) pins on the FPGA in the top level.

    so:

    entity 8255 is
    (
    ...
    8255_port_i : in std_logic;
    8255_port_o : out std_logic;
    8255_port_oe : out std_logic;
    ...
    );

    8255_port_i <= fpga_birdir_port;
    fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Mar 2, 2008
    #3
  4. Shalini Keshavamurthy

    Shalini Guest

    On Mar 3, 4:40 am, Mark McDougall <> wrote:
    > wrote:
    > >> i want to simulate 8255 using vhdl.

    >
    > FYI been done (a few times) before...
    >
    > >> is there any way to configure a port as an I/P or an O/P based on
    > >> certain conditions in d architecture? how do i go abt it?

    > > You'd have to do it using inout ports

    >
    > I'd strongly suggest you don't use inout ports in your 8255 model, but
    > rather use input, output and output-enable ports for each 8255 IO port and
    > then connect them to bidir (inout) pins on the FPGA in the top level.
    >
    > so:
    >
    > entity 8255 is
    > (
    >   ...
    >   8255_port_i    : in std_logic;
    >   8255_port_o    : out std_logic;
    >   8255_port_oe   : out std_logic;
    >   ...
    > );
    >
    > 8255_port_i <= fpga_birdir_port;
    > fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';
    >
    > Regards,
    >
    > --
    > Mark McDougall, Engineer
    > Virtual Logic Pty Ltd, <http://www.vl.com.au>
    > 21-25 King St, Rockdale, 2216
    > Ph: +612-9599-3255 Fax: +612-9599-3266


    thanks Mark
    thanks neha
     
    Shalini, Mar 3, 2008
    #4
  5. Shalini Keshavamurthy

    priyvrat5

    Joined:
    Apr 29, 2009
    Messages:
    1
    8255 Mode_1 VHDL/ Verilog Code.

    Hello!

    Can any body provide me 8255 Mode_1 & Mode_0 VHDL/ Verilog Code.


    Regards
     
    priyvrat5, May 1, 2009
    #5
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