simulating records

[tahder]

hi everyone.

i browsed through a material by gaisler on structured vhdl design method.

i tried his implementation of a counter using record types however, i had problems with its simulation because its input and output ports are of record types. can anyone show me how to create an interface block so that i could simulate this block with ise litesim and eventually synthesize it? the code is shown below.

thanks,
tahder

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package count8_comp is -- component declaration package

type count8_in_type is record
load : std_logic;
count : std_logic;
din : std_logic_vector(7 downto 0);
end;

type count8_out_type is record
dout : std_logic_vector(7 downto 0);
zero : std_logic;
end;

component count8
port (
clk : in std_logic;
d : in count8_in_type;
q : out count8_out_type);
end component;
end count8_comp;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.count8_comp.all;

entity count8 is
port (
clk : in std_logic;
d : in count8_in_type;
q : out count8_out_type);
end;

architecture twoproc of count8 is
type reg_type is record
load : std_logic;
count : std_logic;
zero : std_logic;
cval : std_logic_vector(7 downto 0);
end;
signal r, rin : reg_type;
begin
comb : process(d, r) -- combinational process
variable v : reg_type;
begin
v := r; -- default assignment
v.load := d.load; v.count := d.count; -- overriding assignments
v.zero := ’0’;
if r.count = ’1’ then
v.cval := r.val + 1;
end if; -- module algorithm
if r.load = ’1’ then
v.cval := d.data;
end if;
if v.cval = "00000000" then
v.zero := ’1’;
end if;
rin <= v; -- drive register inputs
q.dout <= r.cval; q.zero <= r.zero; -- drive module outputs
end process;
regs : process(clk) -- sequential process
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;