Simulating testbench waveform error: "No feasible entries for subprogram write"

Discussion in 'VHDL' started by Taras_96, Jul 31, 2005.

  1. Taras_96

    Taras_96 Guest

    Hi everyone

    I'm trying to simulate a module from within Xilinx using Modelsim. I
    have generated a testbench waveform using the inbuilt waveform
    generator. When I double click on either "Simulate Behavioural Model"
    (which opens up a Modelsim window) or "Generate Expected Simulation
    Results" I get the following error:

    "# ** Error: modmultcontrol_test_1.ant(56): No feasible entries for
    subprogram write"

    I have searched on groups and in google for an answer, and from that it
    looks like it has something to do with the subprogram 'write'. My best
    guess is that the waveform generator generates code that uses this
    subprogram, but I'm not sure. The VHDL code is shown below.

    Does anyone have any ideas?

    Thanks

    Taras


    =================================================
    VHDL
    =================================================
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    use work.GlobalConstants.all;

    entity ModmultControl is
    port( CLK : in std_logic;
    RST_MODMULT : in std_logic;
    innerState : out unsigned (COUNTER_BITS downto 0);
    enableInner : out std_logic);
    end ModmultControl;

    architecture RTL of ModmultControl is
    signal innerState_out, nextState : unsigned (COUNTER_BITS downto 0);
    constant FINISH_STATE : unsigned := to_unsigned(N_B_SIZE + 1,
    COUNTER_BITS);
    begin
    innerState <= innerState_out;
    enableInner <= '1' when (RST_MODMULT = '1' or innerState_out /=
    FINISH_STATE) else
    '0';

    -- use Xilinx's template
    combinational: process (innerState_out)
    begin
    if innerState_out = FINISH_STATE then
    nextState <= innerState_out;
    else
    nextState <= innerState_out + 1;
    end if;
    end process;

    sequential: process (CLK)
    begin
    if rising_edge(CLK) then
    if RST_MODMULT = '1' then
    innerState_out <= FINISH_STATE;
    else
    innerState_out <= nextState;
    end if;
    end if;
    end process;


    end RTL;
    Taras_96, Jul 31, 2005
    #1
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  2. Re: Simulating testbench waveform error: "No feasible entries forsubprogram write"

    Taras_96 wrote:

    > I have searched on groups and in google for an answer, and from that it
    > looks like it has something to do with the subprogram 'write'. My best
    > guess is that the waveform generator generates code that uses this
    > subprogram, but I'm not sure. The VHDL code is shown below.


    Consider learning how to write
    your own vhdl testbench to run
    directly on modelsim.
    Here's an example to get
    you started.

    -- Mike Treseler

    http://home.comcast.net/~mike_treseler/test_uart.vhd
    Mike Treseler, Aug 1, 2005
    #2
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  3. Taras_96

    Taras_96 Guest

    Just wondering why this 'feature' of Xilnix doesn't work - it would be
    quite useful for quickly testing a small bit of code. Oh well, I'll
    have to write all of my testbenches I suppose
    Taras_96, Aug 3, 2005
    #3
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