Simulation : Access internal signals

Discussion in 'VHDL' started by Closter, May 3, 2007.

  1. Closter

    Closter Guest

    Hello,

    I create a design with some component. In behavioral simulation I
    want to access to internal bus signals of my component in order to
    save their value into a file.
    I work with modelsim and it allow to look at this signals. But I
    don't know how to save this signals into file.

    Does solutions exists to access internal signals without
    simulating each component of my design separately ?

    Thanks.
     
    Closter, May 3, 2007
    #1
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  2. On 3 May 2007 07:21:26 -0700, Closter <> wrote:

    >Hello,
    >
    > I create a design with some component. In behavioral simulation I
    >want to access to internal bus signals of my component in order to
    >save their value into a file.
    > I work with modelsim


    Lots of possibilities:

    (1)
    Look out ModelSim's documentation for the "SignalSpy" feature.
    It's part of the simulator command language - it is not built in
    to VHDL - but it works well and is fairly easy to use.

    (2)
    Alternatively, use the [log] command to trace all the signals
    of interest to the waveform log file (*.wlf) and then look into
    the "WLF API" which allows you to read data from the waveform
    file using C-language programs.

    (3)
    Finally, consider using Tcl scripting to grab signal values
    using the [examine] command, and then write them to a file
    using plain Tcl. You can do this either by stopping the
    simulator at interesting times, or by (again) logging to the
    waveform file and then using the -time option of the [examine]
    command to look backwards in time into the waveform file.

    I've used (1) and (3) successfully, but have no personal
    experience of (2).

    Good luck.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, May 3, 2007
    #2
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  3. Closter

    Closter Guest

    On 3 mai, 17:57, Jonathan Bromley <>
    wrote:
    > On 3 May 2007 07:21:26 -0700, Closter <> wrote:
    >
    > >Hello,

    >
    > > I create a design with some component. In behavioral simulation I
    > >want to access to internal bus signals of my component in order to
    > >save their value into a file.
    > > I work with modelsim

    >
    > Lots of possibilities:
    >
    > (1)
    > Look out ModelSim's documentation for the "SignalSpy" feature.
    > It's part of the simulator command language - it is not built in
    > to VHDL - but it works well and is fairly easy to use.
    >
    > (2)
    > Alternatively, use the [log] command to trace all the signals
    > of interest to the waveform log file (*.wlf) and then look into
    > the "WLF API" which allows you to read data from the waveform
    > file using C-language programs.
    >
    > (3)
    > Finally, consider using Tcl scripting to grab signal values
    > using the [examine] command, and then write them to a file
    > using plain Tcl. You can do this either by stopping the
    > simulator at interesting times, or by (again) logging to the
    > waveform file and then using the -time option of the [examine]
    > command to look backwards in time into the waveform file.
    >
    > I've used (1) and (3) successfully, but have no personal
    > experience of (2).
    >
    > Good luck.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    Ok,
    Thanks for help
     
    Closter, May 4, 2007
    #3
  4. Closter

    rbelli Guest

    On May 4, 10:05 am, Closter <> wrote:
    > On 3 mai, 17:57, Jonathan Bromley <>
    > wrote:
    >
    >
    >
    > > On 3 May 2007 07:21:26 -0700, Closter <> wrote:

    >
    > > >Hello,

    >
    > > > I create a design with some component. In behavioral simulation I
    > > >want to access to internal bus signals of my component in order to
    > > >save their value into a file.
    > > > I work with modelsim

    >
    > > Lots of possibilities:

    >
    > > (1)
    > > Look out ModelSim's documentation for the "SignalSpy" feature.
    > > It's part of the simulator command language - it is not built in
    > > to VHDL - but it works well and is fairly easy to use.

    >
    > > (2)
    > > Alternatively, use the [log] command to trace all the signals
    > > of interest to the waveform log file (*.wlf) and then look into
    > > the "WLF API" which allows you to read data from the waveform
    > > file using C-language programs.

    >
    > > (3)
    > > Finally, consider using Tcl scripting to grab signal values
    > > using the [examine] command, and then write them to a file
    > > using plain Tcl. You can do this either by stopping the
    > > simulator at interesting times, or by (again) logging to the
    > > waveform file and then using the -time option of the [examine]
    > > command to look backwards in time into the waveform file.

    >
    > > I've used (1) and (3) successfully, but have no personal
    > > experience of (2).

    >
    > > Good luck.
    > > --
    > > Jonathan Bromley, Consultant

    >
    > > DOULOS - Developing Design Know-how
    > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    >
    > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > > ://www.MYCOMPANY.com

    >
    > > The contents of this message may contain personal views which
    > > are not the views of Doulos Ltd., unless specifically stated.

    >
    > Ok,
    > Thanks for help


    I make a different approach to log internal data. I use the following
    method:

    I declare a generic called simulation, like:
    GENERIC(

    simulation : INTEGER := 0
    );
    in all the components in the hierarchy. In the test vhdl I instantiate
    the top vhdl project file with simulation equals 1.

    Internally in the places I want to log the data I use the following
    construction:
    ---------------------------------------------------
    gen_logdata1 : IF(simulation = 1) GENERATE

    logdata1 : logdata
    GENERIC MAP(
    file_name => "saidaPort.dat",
    n_bits => phi_inc_portadora'Length,
    n_elements => 1,
    gerar => simulation
    )
    PORT MAP(
    clk => enable_port,
    enable => enable_true,
    input => phi_inc_portadora
    );

    END GENERATE;
    -----------------------------------------------------

    The code of the logdata is:

    -----------------------------------------------------
    Library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_signed.all;
    use std.textio.all;
    use ieee.std_logic_textio.all;

    ENTITY logdata IS
    GENERIC(
    file_name : string;
    n_bits : INTEGER := 12;
    n_elements : INTEGER := 1;
    gerar : INTEGER := 1
    );
    PORT(
    clk : in std_logic;
    enable : in std_logic := '1';
    input : in std_logic_vector(n_bits * n_elements - 1 downto
    0)
    );
    END logData;

    ARCHITECTURE beh of logdata IS


    BEGIN
    gerar1 : IF (gerar = 1) GENERATE

    PROCESS
    FILE fid2 : TEXT;
    VARIABLE line2 : LINE;
    VARIABLE temp_v : std_logic_vector(((n_bits+3)/4)*4-1 downto 0);
    BEGIN

    file_open(fid2, file_name, WRITE_MODE);

    WHILE TRUE LOOP
    wait until rising_edge(clk) AND enable = '1';

    FOR i in 1 TO n_elements LOOP
    temp_v := (OTHERS => '0');
    temp_v(n_bits-1 downto 0) := input( (i*n_bits - 1)
    downto ((i-1) * n_bits) );
    hwrite(line2, temp_v, RIGHT, n_bits/4+3);
    END LOOP;
    writeline(fid2, line2);
    END LOOP;

    END PROCESS;
    END GENERATE;

    END beh;

    -----------------------------------------------

    I use this code with the modelsim and I can compile it with the XILINX
    ISE without any modifications.
     
    rbelli, May 5, 2007
    #4
  5. Closter

    heliovj

    Joined:
    Dec 10, 2009
    Messages:
    1
    Hi!

    I know this thread is old but...
    I have the same problem and I would like to use the 3rd option: the one using tcl script and the examine command. But I don't know really much about tcl.
    So... someone could help me writting a script that stops the simulator at interesting times (every clock cycle would be ok) and captures the values of a certain internal signal?

    Thanks for help!
     
    heliovj, Dec 10, 2009
    #5
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