simulation and test bench

Discussion in 'VHDL' started by john, Mar 26, 2006.

  1. john

    john Guest

    Hello,

    Can somebody advice me that whats the difference between the simulation
    and test bench. I am using Quatrus these days and it has a simulator. I
    wrote a VHDL program and took it into the simulator, define clock and
    other control signals and started testing my design. Now, somebody told
    me that I need to write a test bench too. I do not know why. Please
    adivce. Thanks
    Regards
    john
    john, Mar 26, 2006
    #1
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  2. john wrote:

    > Can somebody advice me that whats the difference between the simulation
    > and test bench. I am using Quatrus these days and it has a simulator. I
    > wrote a VHDL program and took it into the simulator, define clock and
    > other control signals and started testing my design.


    The Quartus simulator tests a synthesis netlist, not source code.
    Using an HDL simulator like modelsim, I can apply stimulus
    algorithmically using a testbench like this:

    http://home.comcast.net/~mike_treseler/test_uart.vhd

    and it will draw the waveforms for me, like this

    http://home.comcast.net/~mike_treseler/uart_sim.pdf

    > Now, somebody told
    > me that I need to write a test bench too. I do not know why.


    The Quartus simulator is adequate for small designs.
    If you haven't run into its limitations,
    there is no need to change horses yet.


    -- Mike Treseler
    Mike Treseler, Mar 26, 2006
    #2
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  3. john wrote:


    > Now, somebody told
    > me that I need to write a test bench too. I do not know why.


    A testbench is the environment you need to test your design. This means
    at least test stimuli and it is recommended, that checks, if the device
    under test operated well, are also included (automatic verification).

    Do something, that proves, that (hopefully) no bugs are int the
    component. Every function, that is not tested can be seen as "not working".

    Ralf
    Ralf Hildebrandt, Mar 26, 2006
    #3
  4. john

    Andy Peters Guest

    john wrote:
    > Can somebody advice me that whats the difference between the simulation
    > and test bench. I am using Quatrus these days and it has a simulator. I
    > wrote a VHDL program and took it into the simulator, define clock and
    > other control signals and started testing my design. Now, somebody told
    > me that I need to write a test bench too. I do not know why. Please
    > adivce. Thanks


    See http://janick.bergeron.com/wtb/wtb2/

    -a
    Andy Peters, Mar 29, 2006
    #4
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