Simulation in modelsim.... Multiple Drivers.......

Discussion in 'VHDL' started by CODE_IS_BAD, Apr 21, 2005.

  1. CODE_IS_BAD

    CODE_IS_BAD Guest

    Hi all...
    i have been trying to simulate some code in which there is a data bus

    that is declared to be of INOUT type. I have simulated my VHDL code and

    for both read and write operations it works fine, also the data bus
    gets tri-stated (Z) when not in use.
    Now this simulation was done by directly putting the values of signals

    in the ModelSim environment. Then I thought to write a testbench to
    simulate the same. In this case when I write some data on the databus
    it does not get tri-stated when not in use. So i tried to debug the
    problem and found that since in my testbench I am forcing some value on

    the bus say '3B' and also in code i force 'Z' when not in use, then
    STD_LOGIC being a resolved type resolves the value and gives '3B' since

    'Z' has got least priority.
    Why it worked directly on ModelSim environment was bcoz i was
    "Depositing" the value on bus and not "Freezing" it. If i freeze the
    value there then in that case also i cud not make the bus tri-stated.


    So i would like to know how in our testbench we can write code such
    that i can see all the correct results. I think in practice this will
    work fine but it's better if in simulation also we can see the desired
    results. Hope somebody can help. Thanx a lot
    PUNEET
     
    CODE_IS_BAD, Apr 21, 2005
    #1
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