simulation limit

Discussion in 'VHDL' started by JSreeniv, Dec 7, 2009.

  1. JSreeniv

    JSreeniv Guest

    Hi all,

    I have a query regarding to the post route simulation(timing
    simulation) using Modelsim, presently i am using 6.4 PE.
    In first i am done Functional simulation using VHDL test bench
    implementation, and when "End of Test" assertion reached and
    simulator will stop from assertion Failure condition; now i got let
    say end time of simulation is 10 us.

    Now loaded necessary files to run timing simulation; now i want to
    know how to decide to give end of simulation time to run; where as
    this timing simulation will take account all the gates, paths
    etc..delays. so appending on the time from where i got functional
    simulation is fine or need to have some analysis? To give end run time
    simulation.

    Please give some exposure on this issue..
    JSreeniv, Dec 7, 2009
    #1
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  2. JSreeniv

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    you can add an "assertion" like this to the very end of the test bench, just to get a final message:
    Code:
    assert false report "end of testbench" severity note;
    joris, Dec 7, 2009
    #2
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  3. JSreeniv wrote:

    > Now loaded necessary files to run timing simulation; now i want to
    > know how to decide to give end of simulation time to run; where as
    > this timing simulation will take account all the gates, paths
    > etc..delays. so appending on the time from where i got functional
    > simulation is fine or need to have some analysis? To give end run time
    > simulation.


    If I use the same testbench, the sim time is the same
    but the coffee drinking time may be ten times longer.

    By the way, a gate sim is a test of your
    tools, rules and testbench, not your design.

    -- Mike Treseler
    Mike Treseler, Dec 7, 2009
    #3
  4. On 7 Dez., 18:40, Mike Treseler <> wrote:
    > JSreeniv wrote:
    > > Now loaded necessary files to run timing simulation; now i want to
    > > know how to decide to give end of simulation time to run; where as
    > > this timing simulation will take account all the gates, paths
    > > etc..delays. so appending on the time from where i got functional
    > > simulation is fine or need to have some analysis? To give end run time
    > > simulation.

    >
    > If I use the same testbench, the sim time is the same
    > but the coffee drinking time may be ten times longer.
    >
    > By the way, a gate sim is a test of your
    > tools, rules and testbench, not your design.


    You should add your skill in using this tools ;).
    Too often happens that simualtion shows an error made in timing
    analysis not by tool but by developer.

    regards Thomas
    Thomas Stanka, Dec 8, 2009
    #4
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