Simulation of Xilinx Rocket IO Instance

Discussion in 'VHDL' started by kedarpapte@gmail.com, Mar 6, 2006.

  1. Guest

    Hello All,

    I want to use Xilinx v2p or v4 rocket IOs in one of my designs.
    right now I am using Xilinx webpack 8.1 and modelsim se/pe.

    can any body tell me that if I generate a rocket IO instance (without
    8b10b and crc) as a simple serdes How do I simulate it...?

    Does the Rocket IO Instance has any output pins for PLL Locked
    signals...?

    I am trying to simulate a transmitter by a simple test bench as to
    provide reset, clock and 8-bit parallel data, but nothing is coming out
    on serial tx pin.

    Please guide me .
    Thanks in advance.

    Regards,
    Kedar
     
    , Mar 6, 2006
    #1
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  2. Guest

    , Mar 7, 2006
    #2
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  3. Guest

    thanks for the zip file I will try and run that simulation
    but when I open the project in ISE I am not able to see some of the
    instanciated parts like
    aurora_module_i_1
    standard_cc_module_i_1
    aurora_module_i_2
    standard_cc_module_i_2

    from where I should add this...?

    please help me

    Thanks & Regards
    Kedar
     
    , Mar 7, 2006
    #3
  4. Paul Hartke Guest

    You need to generate these files from Coregen. It is explained in the
    Aurora_QuickStart.pdf document in the zip file.

    Paul

    wrote:
    >
    > thanks for the zip file I will try and run that simulation
    > but when I open the project in ISE I am not able to see some of the
    > instanciated parts like
    > aurora_module_i_1
    > standard_cc_module_i_1
    > aurora_module_i_2
    > standard_cc_module_i_2
    >
    > from where I should add this...?
    >
    > please help me
    >
    > Thanks & Regards
    > Kedar
     
    Paul Hartke, Mar 7, 2006
    #4
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