Simulation problem in VHDL Simili from Symphony EDA package.

Discussion in 'VHDL' started by Daniel, Oct 17, 2006.

  1. Daniel

    Daniel Guest

    How do I simulate CLOCK signal?

    I'm previous user of ActiveHDL where I could simply choose "stimulators" -
    clk, hotkey, forse '0', '1',...

    I can't find anything like this in VHDL Simili's Sonata simulator.

    Do I have to write a code for CLK signal? I read the official docs, but
    couldn't find any information about this,...

    Thanks.
     
    Daniel, Oct 17, 2006
    #1
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  2. Daniel

    Ajeetha Guest

    Your best bet will be to write one line code inside your "testbench"
    as:

    signal clock : std_logic := '0';
    .....
    clock <= not clock after 10 ns;

    HTH
    Ajeetha, CVC
    www.noveldv.com

    Daniel wrote:
    > How do I simulate CLOCK signal?
    >
    > I'm previous user of ActiveHDL where I could simply choose "stimulators" -
    > clk, hotkey, forse '0', '1',...
    >
    > I can't find anything like this in VHDL Simili's Sonata simulator.
    >
    > Do I have to write a code for CLK signal? I read the official docs, but
    > couldn't find any information about this,...
    >
    > Thanks.
     
    Ajeetha, Oct 17, 2006
    #2
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  3. Daniel

    Andy Guest

    You've just hit upon the main reason not to use such simulator commands
    for stimulus: they're not portable between different simulators!

    Better to stimulte from a vhdl testbench wrapper around your
    unit-under-test, with a signal assignment such as:

    signal clk : std_logic := '1'; -- init val is ok for sim!
    signal stop : boolean := false;
    constant clk_prd : time : 10 ns; -- change as requiresd
    constant sim_time : time := 100 * clk_prd; -- change as required
    ....
    clk <= not clk after clk_prd / 2 when not stop;

    stop <= true after sim_time; -- stop clock

    This will work from any vhdl simulator.

    Andy


    Daniel wrote:
    > How do I simulate CLOCK signal?
    >
    > I'm previous user of ActiveHDL where I could simply choose "stimulators" -
    > clk, hotkey, forse '0', '1',...
    >
    > I can't find anything like this in VHDL Simili's Sonata simulator.
    >
    > Do I have to write a code for CLK signal? I read the official docs, but
    > couldn't find any information about this,...
    >
    > Thanks.
     
    Andy, Oct 18, 2006
    #3
  4. Daniel

    pitarda Guest

    I will take you advice and try to write the code this way.

    Thanks.


    Andy je napisal:
    > You've just hit upon the main reason not to use such simulator commands
    > for stimulus: they're not portable between different simulators!
    >
    > Better to stimulte from a vhdl testbench wrapper around your
    > unit-under-test, with a signal assignment such as:
    >
    > signal clk : std_logic := '1'; -- init val is ok for sim!
    > signal stop : boolean := false;
    > constant clk_prd : time : 10 ns; -- change as requiresd
    > constant sim_time : time := 100 * clk_prd; -- change as required
    > ...
    > clk <= not clk after clk_prd / 2 when not stop;
    >
    > stop <= true after sim_time; -- stop clock
    >
    > This will work from any vhdl simulator.
    >
    > Andy
    >
    >
    > Daniel wrote:
    > > How do I simulate CLOCK signal?
    > >
    > > I'm previous user of ActiveHDL where I could simply choose "stimulators" -
    > > clk, hotkey, forse '0', '1',...
    > >
    > > I can't find anything like this in VHDL Simili's Sonata simulator.
    > >
    > > Do I have to write a code for CLK signal? I read the official docs, but
    > > couldn't find any information about this,...
    > >
    > > Thanks.
     
    pitarda, Oct 18, 2006
    #4
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