Simulation Problem

Discussion in 'VHDL' started by Naimesh, Jun 29, 2004.

  1. Naimesh

    Naimesh Guest

    I am using XILINX ISE 6.1 and Modelsim for simulation. when I run the
    simulation I get follwoing warning.

    Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
    result will be 'X'(es).
    # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1
    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    operand, the result will be 'X'(es).
    # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1

    Now when I see the WAVE window I dont get any X'es in any signal. How
    do I find out which signal is creating the problem.

    Thanks for any help.

    Naimesh
     
    Naimesh, Jun 29, 2004
    #1
    1. Advertising

  2. Naimesh wrote:

    > I am using XILINX ISE 6.1 and Modelsim for simulation. when I run the
    > simulation I get follwoing warning.
    >
    > Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
    > result will be 'X'(es).
    > # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1
    > # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    > operand, the result will be 'X'(es).
    > # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1
    >
    > Now when I see the WAVE window I dont get any X'es in any signal. How
    > do I find out which signal is creating the problem.


    It's not a problem. Note that they are warnings and occur at time = 0.
    This is typically the result of doing an integer conversion (either
    directly or implicitly) on an std_logic_vector or unsigned/signed in
    combinational logic.

    e.g. n:1 mux
    out <= input_vector(to_integer(unsigned(select_vector));

    These vectors are 'X' at time=0, hence the warnings. It is possible to
    disable them but unless there are a huge number of them, I usually just
    ignore them.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Jun 29, 2004
    #2
    1. Advertising

  3. Naimesh

    ALuPin Guest

    (Naimesh) wrote in message news:<>...
    > I am using XILINX ISE 6.1 and Modelsim for simulation. when I run the
    > simulation I get follwoing warning.
    >
    > Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
    > result will be 'X'(es).
    > # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1
    > # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    > operand, the result will be 'X'(es).
    > # Time: 0 ps Iteration: 0 Instance: /testbenchcmedmain/uut/dpll1
    >
    > Now when I see the WAVE window I dont get any X'es in any signal. How
    > do I find out which signal is creating the problem.
    >
    > Thanks for any help.
    >
    > Naimesh



    Are you sure that you displayed all signals?

    Are your registered signals resetted so that they start up in a defined
    state?
     
    ALuPin, Jun 29, 2004
    #3
  4. Naimesh

    Naimesh Guest

    (ALuPin) wrote in message news:<>...

    I think I displayed all the signals and all are reseted with the RESET signal.

    The entity in which I m getting error i.e. Instance: /testbenchcmedmain/uut/dpll1


    does have a integer conversion from std_logic_vector. How do I remove it.


    > Are you sure that you displayed all signals?
    >
    > Are your registered signals resetted so that they start up in a defined
    > state?
     
    Naimesh, Jun 30, 2004
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Andy
    Replies:
    5
    Views:
    588
  2. Andy Botterill

    VHDL/Verilog simulation problem

    Andy Botterill, Nov 4, 2003, in forum: VHDL
    Replies:
    0
    Views:
    1,469
    Andy Botterill
    Nov 4, 2003
  3. Tomek
    Replies:
    8
    Views:
    893
    Tomek
    Jul 28, 2004
  4. Urban Stadler

    simulation problem

    Urban Stadler, Jul 24, 2004, in forum: VHDL
    Replies:
    1
    Views:
    1,171
    Tim Hubberstey
    Jul 24, 2004
  5. jasperng
    Replies:
    0
    Views:
    1,328
    jasperng
    Nov 27, 2008
Loading...

Share This Page