Simulation problem

Discussion in 'VHDL' started by haiko, Jun 23, 2011.

  1. haiko

    haiko

    Joined:
    Jun 23, 2011
    Messages:
    1
    Hello everybody!
    I have one big problom can somebody help me?

    I write the folowing VHDL code but it hes problem with simulation.
    with compiling evrything is ok. But when i trying simulate it ModelSim givs the folowing messige. (Warning: (vsim-3473) Component instance "a1 : lebel" is not bound.)

    What is the problem what i have to do for make this problem?

    entity basic is
    port(input : in bit;
    output: out bit);
    end basic;

    use work.all;
    architecture B1 of basic is
    begin
    output <= not input;
    end B1;
    --*********************************************************
    --*********************************************************
    --library ieee;
    --use ieee.std_logic_1164.all;
    entity second is end second;

    use work.all;
    architecture B2 of second is
    component lebel is
    port (in_1 : in bit; out_1 : out bit);
    end component;

    signal in_1, out_1 :bit;
    begin
    a1: lebel port map(in_1, out_1);
    end B2;
    --*********************************************************
    --*********************************************************
    --library ieee;
    --use ieee.std_logic_1164.all;
    --library work.all;
    configuration config of second is
    for B2
    for a1: lebel
    use entity work.basic(B1)
    port map (in_1, out_1);
    end for;
    end for;
    end config;
    --*********************************************************
    --*********************************************************
    haiko, Jun 23, 2011
    #1
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