simulation problems

Discussion in 'VHDL' started by FPGA, Jan 4, 2008.

  1. FPGA

    FPGA Guest

    I havw writtent the following code. It compiles correctly. When i run
    the simulation it just stops and points to this statement
    variable result : unsigned(bw-1 downto 0);

    The code and test bench are as below
    -- VHDL library declarations
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;

    -- entity declaration
    entity floor_top is
    generic ( bwin : integer:= 6; bwout : integer := 3);
    port(
    x : IN unsigned(bwin-1 downto 0);
    bw : IN integer;
    y : OUT unsigned(bwout-1 downto 0)
    );
    END floor_top;

    -- architecture declaration
    architecture behavioral of floor_top is

    -- function declaration
    function floor( x: unsigned; bw: integer) return unsigned is
    variable result : unsigned(bw-1 downto 0);
    begin
    result := resize(x,bw);
    return result;
    end floor;

    begin

    y <= floor(x,bw);

    end behavioral;


    test bench is as follows =>

    LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;

    ENTITY util_tb IS
    -- testbench entity is ALWAYS EMPTY
    END util_tb;

    ARCHITECTURE tb OF util_tb IS

    -- local signal declaration
    SIGNAL x : unsigned(5 downto 0) ;
    SIGNAL bw : integer;
    SIGNAL y : unsigned(2 DOWNTO 0);

    -- component declaration
    COMPONENT floor_top IS
    generic ( bwin : integer:= 6; bwout : integer := 3);
    port(
    x : IN unsigned(bwin-1 downto 0);
    bw : IN integer;
    y : OUT unsigned(bwout-1 downto 0)
    );
    END COMPONENT;

    BEGIN
    UUT : floor_top
    PORT MAP(
    x => x,
    bw => bw,
    y => y
    );

    -- apply inputs to monitor outputs
    x <= "101101" AFTER 0 ns,
    "001001" AFTER 15 ns,
    "111001" AFTER 25 ns;

    bw <= 3 AFTER 0 ns;

    END tb;
    FPGA, Jan 4, 2008
    #1
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  2. FPGA

    FPGA Guest

    On Jan 4, 8:10 am, FPGA <> wrote:
    > I havw writtent the following code. It compiles correctly. When i run
    > the simulation it just stops and points to this statement
    > variable result   :   unsigned(bw-1 downto 0);
    >
    > The code and test bench are as below
    > -- VHDL library declarations
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.std_logic_unsigned.all;
    > use ieee.numeric_std.all;
    >
    > -- entity declaration
    > entity floor_top is
    > generic ( bwin : integer:= 6; bwout : integer := 3);
    > port(
    >         x   :   IN unsigned(bwin-1 downto 0);
    >         bw  :   IN integer;
    >              y   :   OUT unsigned(bwout-1 downto 0)
    >     );
    > END floor_top;
    >
    > -- architecture declaration
    > architecture behavioral of floor_top is
    >
    >    -- function declaration
    >    function floor( x: unsigned; bw: integer) return unsigned is
    >       variable result   :   unsigned(bw-1 downto 0);
    >    begin
    >       result   :=   resize(x,bw);
    >       return result;
    >    end floor;
    >
    > begin
    >
    >        y   <=   floor(x,bw);
    >
    > end behavioral;
    >
    > test bench is as follows =>
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > use ieee.std_logic_unsigned.all;
    > use ieee.numeric_std.all;
    >
    > ENTITY util_tb IS
    >        -- testbench entity is ALWAYS EMPTY
    > END util_tb;
    >
    > ARCHITECTURE tb OF util_tb IS
    >
    >    -- local signal declaration
    >    SIGNAL x    :   unsigned(5 downto 0) ;
    >    SIGNAL bw   :   integer;
    >    SIGNAL y    :   unsigned(2 DOWNTO 0);
    >
    >     -- component declaration
    >    COMPONENT floor_top IS
    >    generic ( bwin : integer:= 6; bwout : integer := 3);
    >    port(
    >            x   :   IN unsigned(bwin-1 downto 0);
    >            bw  :   IN integer;
    >                 y   :   OUT unsigned(bwout-1 downto 0)
    >        );
    >    END COMPONENT;
    >
    >   BEGIN
    >         UUT : floor_top
    >         PORT MAP(
    >                      x   =>   x,
    >                      bw  =>   bw,
    >                      y   =>   y
    >                  );
    >
    >             -- apply inputs to monitor outputs
    >             x    <=   "101101" AFTER 0 ns,
    >                       "001001" AFTER 15 ns,
    >                       "111001" AFTER 25 ns;
    >
    >                  bw    <=   3 AFTER 0 ns;
    >
    > END tb;


    The error i get is as follows
    # ** Fatal: (vsim-3965) Memory Allocation is too large. Please check
    your usage.
    # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/
    Modeltech_pe_edu_6.3c/examples/floor_top.vhd
    # Fatal error in Subprogram floor at C:/Modeltech_pe_edu_6.3c/examples/
    floor_top.vhd line 47

    line 47 in my code is variable result : unsigned(bw-1 downto 0);
    FPGA, Jan 4, 2008
    #2
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  3. FPGA

    Tricky Guest

    > bw <= 3 AFTER 0 ns;

    This is your problem. Assigning a value "AFTER 0 ns" in reality means
    it wont assign the value until the 2nd delta cycle, as it incurs a 1
    delta cycle delay. this means "bw" is unassigned for the 1st delta
    cycle, and it will be trying to resize the unsigned x with
    INTEGER'LOW, which is something like -2.147Billion

    IE. its probably trying to make the unisgned variable "result" 2.147
    billion bits wide. I doubt you have enough memory for that.

    to fix: either remove the "AFTER 0 ns" or give BW an initial value in
    the signal declarations ie:
    signal bw : integer := 3;
    Tricky, Jan 4, 2008
    #3
  4. On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <>
    wrote:

    >I havw writtent the following code. It compiles correctly. When i run
    >the simulation it just stops and points to this statement
    >variable result : unsigned(bw-1 downto 0);

    It would.

    >The code and test bench are as below
    >-- VHDL library declarations
    >library ieee;
    >use ieee.std_logic_1164.all;
    >use ieee.std_logic_unsigned.all;

    This is NOT a standard library. Don't use it.
    >use ieee.numeric_std.all;

    This is a standard library and works well.

    What you have done here is introduce two different incompatible
    definitions of "unsigned"...
    - Brian
    Brian Drummond, Jan 4, 2008
    #4
  5. FPGA

    FPGA Guest

    I fixed the problem which I had initially.
    I have a new one now :)

    ** Fatal: (vsim-3420) Array lengths do not match. Left is 3 (2 downto
    0). Right is 0 (-1 downto 0 (null array)).
    # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/
    Modeltech_pe_edu_6.3c/examples/floor_top.vhd
    # Fatal error in Architecture behavioral at C:/Modeltech_pe_edu_6.3c/
    examples/floor_top.vhd line 55
    #

    line 55 is
    y <= floor(x,bw);

    Please help

    On Jan 4, 9:39 am, Brian Drummond <>
    wrote:
    > On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <>
    > wrote:
    >
    > >I havw writtent the following code. It compiles correctly. When i run
    > >the simulation it just stops and points to this statement
    > >variable result   :   unsigned(bw-1 downto 0);

    >
    > It would.
    >
    > >The code and test bench are as below
    > >-- VHDL library declarations
    > >library ieee;
    > >use ieee.std_logic_1164.all;
    > >use ieee.std_logic_unsigned.all;

    >
    > This is NOT a standard library. Don't use it.>use ieee.numeric_std.all;
    >
    > This is a standard library and works well.
    >
    > What you have done here is introduce two different incompatible
    > definitions of "unsigned"...
    > - Brian
    FPGA, Jan 4, 2008
    #5
  6. FPGA

    Andy Guest

    On Jan 4, 9:00 am, FPGA <> wrote:
    > I fixed the problem which I had initially.
    > I have a new one now :)
    >
    > ** Fatal: (vsim-3420) Array lengths do not match. Left is 3 (2 downto
    > 0). Right is 0 (-1 downto 0 (null array)).
    > # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/
    > Modeltech_pe_edu_6.3c/examples/floor_top.vhd
    > # Fatal error in Architecture behavioral at C:/Modeltech_pe_edu_6.3c/
    > examples/floor_top.vhd line 55
    > #
    >
    > line 55 is
    > y <= floor(x,bw);
    >
    > Please help
    >
    > On Jan 4, 9:39 am, Brian Drummond <>
    > wrote:
    >
    > > On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <>
    > > wrote:

    >
    > > >I havw writtent the following code. It compiles correctly. When i run
    > > >the simulation it just stops and points to this statement
    > > >variable result : unsigned(bw-1 downto 0);

    >
    > > It would.

    >
    > > >The code and test bench are as below
    > > >-- VHDL library declarations
    > > >library ieee;
    > > >use ieee.std_logic_1164.all;
    > > >use ieee.std_logic_unsigned.all;

    >
    > > This is NOT a standard library. Don't use it.>use ieee.numeric_std.all;

    >
    > > This is a standard library and works well.

    >
    > > What you have done here is introduce two different incompatible
    > > definitions of "unsigned"...
    > > - Brian


    For some reason, and I'm not sure why yet, bw is starting out at
    zero. The earlier comments about the assignment taking place at 0 + 1
    or more deltas is correct, but as per the previous comment, I would
    have expected the initial value on bw to be integer'low which is at
    least -(2**31-1).

    There are a couple of ways to fix the problem, the simplest it to
    explicitly initialize bw to 3 in its declaration.

    However, the bw parameter shouldn't really be associated with a signal
    or even a variable, since it sets the width of the return value, and
    that must match the static width of the signal to which the result is
    being assigned. Therefore, bw should probably be a constant, or could
    also be replaced by y'length in the call to floor.

    I would also declare the bw constant to be of type positive, since you
    know it has to be greater than zero. If it were a generic, I would
    certainly declare it with type positive to ensure that nobody tried to
    set it to zero or negative.

    On the subject of generics, I noticed the comment in your code that
    test bench entities are ALWAYS EMPTY. Such is not the case. It can be
    very useful to put generic declarations on the test bench entity, with
    default values, so that they can be overridden via command-line option
    when compiled/elaborated/simulated. This can be used to run different
    test cases without changing the code.

    Hope this helps,

    Andy
    Andy, Jan 4, 2008
    #6
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