Simulation vs. Synthesis Code?

[Jonathan Ross]

Is there any way for me to emit different code depending on whether
I'm simulating or synthesizing? I have a constant that I assign a much
smaller value to during synthesis, but right now I have to remember to
manually change my code each time.

 

[Andy]

Is there any way for me to emit different code depending on whether
I'm simulating or synthesizing? I have a constant that I assign a much
smaller value to during synthesis, but right now I have to remember to
manually change my code each time.

Probably the easiest way is to use a generic on the top level of the
unit under test (which should be instantiated in your testbench). On
the UUT entity, give the generic a default value that you want to use
for synthesis. When you instantiate the entity in the testbench, you
can give it a different value in the generic map.

Another variation of this takes advantage of most tools' ability to
set the value of top level generics via gui or command-line options.
So your synthesis tool can set a top level (UUT) generic to one value,
and if your testbench plumbs that generic up to its top level entity,
the simulator can set it to a different value.

Andy

 

[Jonathan]

Probably the easiest way is to use a generic on the top level of the
unit under test (which should be instantiated in your testbench). On
the UUT entity, give the generic a default value that you want to use
for synthesis. When you instantiate the entity in the testbench, you
can give it a different value in the generic map.

Another variation of this takes advantage of most tools' ability to
set the value of top level generics via gui or command-line options.
So your synthesis tool can set a top level (UUT) generic to one value,
and if your testbench plumbs that generic up to its top level entity,
the simulator can set it to a different value.

Andy

Thanks Andy. Coming from a C++ background I'm accustomed to a large
quantity of predefined define values that can be used to taylor my
code. In the absence of built in constructs, is it possible to define
a constant in my testbench or the highest level of my VHDL for
synthesis to give it a true or false value depending on whether it's
synthesis or not, and then use a generate statement for the constant?

 

[KJ]

You can set the value of a constant in a trivial function...

function init_const return integer is

Minor nit, since there are no parameters to the function the
declaration should be

impure function init_const return integer is

KJ

 

[Andy Rushton]

Minor nit, since there are no parameters to the function the
declaration should be

impure function init_const return integer is

KJ

No it shouldn't. Impure means it either has side-effects beyond its
return value or returns different values for the same parameters. It
doesn't mean parameterless. This function does not have side effects and
always returns the same value, so it is pure.

 

[Martin Thompson]

Thanks Andy. Coming from a C++ background I'm accustomed to a large
quantity of predefined define values that can be used to taylor my
code. In the absence of built in constructs, is it possible to define
a constant in my testbench or the highest level of my VHDL for
synthesis to give it a true or false value depending on whether it's
synthesis or not, and then use a generate statement for the
constant?

You can create a package with the following constant in it (which is a
bit ugly, but does the job...)

constant in_simulation : boolean := false
--synthesis translate_off
or true
--synthesis translate_on
;

Cheers,
Martin