simulation working , synthesis causing problems

Discussion in 'VHDL' started by sandeep, May 11, 2006.

  1. sandeep

    sandeep Guest

    Hi,

    I am simualting a UART in VHDL for a PCI bus frontend. It's running
    perfectly in simualtion but doesnot run on the actual chip.

    I made the following observations.

    In simulation, the TX line is at high when not transmitting any data
    value. When I write a data value with a write signal, it transmits it
    and then returns back to the HIGH state. UART_RDY is asserted at this
    time, which indicates that the UART is ready for the next data value.
    Hence in simulation its working perfectly.

    When I synthesis the same into a chip, the TX line is never HIGH when
    the chip powers ON. It is transmitting some random junk value, and
    hence the UART_RDY is never asserted. Which in turn does not allow me
    to load in a data value into the UART from the PCI bus. I want to hold
    the TX line HIGh when the chip powers up, so that I can load in data
    into the UART.

    I guess what I am saying is that at POWER ON, do I need ("ZZZZ ZZZZ")
    or on the TX line. Is there any way I can do it in VHDL.

    Thank you,

    Sandeep
     
    sandeep, May 11, 2006
    #1
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