sine and cosine wave generation

Discussion in 'VHDL' started by FPGA, Jan 14, 2008.

  1. FPGA

    FPGA Guest

    Can anyone give guidelines on how to generate sine and cosine wave in
    VHDL?
    FPGA, Jan 14, 2008
    #1
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  2. FPGA

    Jon Beniston Guest

    On 14 Jan, 15:36, FPGA <> wrote:
    > Can anyone give guidelines on how to generate sine and cosine wave in
    > VHDL?


    Use a look-up table.

    Cheers,
    Jon
    Jon Beniston, Jan 14, 2008
    #2
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  3. FPGA schrieb:
    > Can anyone give guidelines on how to generate sine and cosine wave in
    > VHDL?


    A very common technique is a look-up table.

    Ralf
    Ralf Hildebrandt, Jan 14, 2008
    #3
  4. FPGA

    FPGA Guest

    On Jan 14, 10:43 am, Ralf Hildebrandt <> wrote:
    > FPGA schrieb:
    >
    > > Can anyone give guidelines on how to generate sine and cosine wave in
    > > VHDL?

    >
    > A very common technique is a look-up table.
    >
    > Ralf


    Could you please explain in more detail
    FPGA, Jan 14, 2008
    #4
  5. FPGA

    Kris Vorwerk Guest

    Kris Vorwerk, Jan 14, 2008
    #5
  6. On 14 Jan., 16:36, FPGA <> wrote:
    > Can anyone give guidelines on how to generate sine and cosine wave in
    > VHDL?


    You can build a numerical oscillator:

    Initialization:
    sin[0] = 1;
    cos[0] = 0;

    Iteration:
    sin[t] = sin[t-1]-cos[t-1]*k;
    cos[t] = cos[t-1]+sin[t-1]*k;

    The Frequency depends on k. If k is 1/2**k you do not even net a
    multiplier.

    This only works for a continues sequence of values. If you need values
    in random
    order you must use a lookup table or CORDIC. Both are available as
    cores in ISE.

    Kolja Sulimma
    cronologic ohg
    comp.arch.fpga, Jan 14, 2008
    #6
  7. FPGA

    Symon Guest

    "FPGA" <> wrote in message
    news:...
    > Can anyone give guidelines on how to generate sine and cosine wave in
    > VHDL?


    library IEEE;
    use IEEE.MATH_REAL.all;
    signal x,y : real;begin x <= sin(y);end;HTH., Syms.
    Symon, Jan 14, 2008
    #7
  8. FPGA

    Arlet Ottens Guest

    comp.arch.fpga wrote:
    > On 14 Jan., 16:36, FPGA <> wrote:
    >> Can anyone give guidelines on how to generate sine and cosine wave in
    >> VHDL?

    >
    > You can build a numerical oscillator:
    >
    > Initialization:
    > sin[0] = 1;
    > cos[0] = 0;
    >
    > Iteration:
    > sin[t] = sin[t-1]-cos[t-1]*k;
    > cos[t] = cos[t-1]+sin[t-1]*k;
    >
    > The Frequency depends on k. If k is 1/2**k you do not even net a
    > multiplier.
    >
    > This only works for a continues sequence of values. If you need values
    > in random
    > order you must use a lookup table or CORDIC. Both are available as
    > cores in ISE.
    >
    > Kolja Sulimma
    > cronologic ohg


    If you slightly modify the iteration, like this:

    sin[t] = sin[t-1] - cos[t-1] * k;
    cos[t] = cos[t-1] + sin[t] * k;

    then the solution doesn't suffer from accumulating rounding errors, at
    the cost of some distortion.
    Arlet Ottens, Jan 14, 2008
    #8
  9. FPGA

    FPGA Guest

    On Jan 14, 1:38 pm, Arlet Ottens <> wrote:
    > comp.arch.fpga wrote:
    > > On 14 Jan., 16:36, FPGA <> wrote:
    > >> Can anyone give guidelines on how to generate sine and cosine wave in
    > >> VHDL?

    >
    > > You can build a numerical oscillator:

    >
    > > Initialization:
    > > sin[0] = 1;
    > > cos[0] = 0;

    >
    > > Iteration:
    > > sin[t] = sin[t-1]-cos[t-1]*k;
    > > cos[t] = cos[t-1]+sin[t-1]*k;

    >
    > > The Frequency depends on k. If k is 1/2**k you do not even net a
    > > multiplier.

    >
    > > This only works for a continues sequence of values. If you need values
    > > in random
    > > order you must use a lookup table or CORDIC. Both are available as
    > > cores in ISE.

    >
    > > Kolja Sulimma
    > > cronologic ohg

    >
    > If you slightly modify the iteration, like this:
    >
    > sin[t] = sin[t-1] - cos[t-1] * k;
    > cos[t] = cos[t-1] + sin[t] * k;
    >
    > then the solution doesn't suffer from accumulating rounding errors, at
    > the cost of some distortion.- Hide quoted text -
    >
    > - Show quoted text -


    Thanks all for your help.
    FPGA, Jan 14, 2008
    #9
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