single wire serial comms module

[Tim McCoy]

Hey all,

I'm coding a module to perform serial comms with an external sensor device
I have, but need the ability to clock data to the destination device, and
then the same wire is used by the secondary microcontroller to drive back
the result of a register read.

So for clarity:
write strategey: send address (FPGA as driver), send data (FPGA as driver)

read strategy: send address (FPGA as driver), receive response data
(external microcontroller as driver)

This is a complete two-pin system, with a CLK and SDIO line. What I
basically need to do is have a pin with "inout" bevahiour, but I cant seem
to get a simulateable design (behavioural or post-synthesis).

I'm currently trying the following dumb approach...

---------
entity sdiocontrol is
Port ( fromFPGA : in std_logic;
direction : in std_logic;
SDIO : inout std_logic;
toFPGA : out std_logic);
end sdiocontrol;

architecture Behavioral of sdiocontrol is

begin
sdiocontrol : process(direction, fromFPGA)
begin
if direction = '0' then
SDIO <= fromFPGA;
else
toFPGA <= SDIO;
end if;
end process sdiocontrol;

end Behavioral;

---------
Any suggestions?

Cheers

Tim
--
"Linux... because rebooting is for adding new hardware!"

http://home.swiftdsl.com.au/~tmccoy
MSN: (e-mail address removed)
ICQ: 160341067

 

[Damien Manoeuvre]

Any suggestions?

SDIO <= fromFPGA when (direction = '0') else 'Z';
toFPGA <= SDIO;

 

[Tim McCoy]

SDIO <= fromFPGA when (direction = '0') else 'Z';
toFPGA <= SDIO;

When simulated at a behavioral level, this results in unknown
levels on the SDIO output pin when the fromFPGA signal is being driven
from low to high.

I'm using the testbench waveform generator within the Xilinx WebPack - is
this likely an issue within the simulation tools?

Cheers

Tim

--
"Linux... because rebooting is for adding new hardware!"

http://home.swiftdsl.com.au/~tmccoy
MSN: (e-mail address removed)
ICQ: 160341067

 

[Andy Peters]

When simulated at a behavioral level, this results in unknown
levels on the SDIO output pin when the fromFPGA signal is being driven
from low to high.

I'm using the testbench waveform generator within the Xilinx WebPack - is
this likely an issue within the simulation tools?

it is, if the waveform generator doesn't know how to drive tristates.
Your test bench must assign SDIO in the same manner as in the FPGA,
e.g.,

SDIO <= fromTestBench when (direction = '1') else 'Z';
fromTestBench <= SDIO;

-a

 

[Tim McCoy]

it is, if the waveform generator doesn't know how to drive tristates.

Your test bench must assign SDIO in the same manner as in the FPGA,
e.g.,

SDIO <= fromTestBench when (direction = '1') else 'Z';
fromTestBench <= SDIO;

-a

Okay, here are the basic test bench waveform files - I'm not sure that I'm
making the right assignments in the directions. I'm trying to test it by
asserting nothing to the SDIO line when direction = '0', to let it
simulate the output being driven by the FPGA.

Then when direction = '1', I'm trying to set a bit waveform on the input
(blue) section of the SDIO line within the direction = '1' section. But
this results in undefined and incorrect levels on toFPGA.

http://home.swiftdsl.com.au/~tmccoy/random/images/xilinx_testbench1.png
http://home.swiftdsl.com.au/~tmccoy/random/images/xilinx_testbench2.png

....the above simulations show that SDIO is being asserted to the high
impedance state correctly, but when I try and put transitions on the SDIO
pin, it all gets strange.

Is there some documentation somewhere about simulating inouts?

Cheers

Tim

--
"Linux... because rebooting is for adding new hardware!"

http://home.swiftdsl.com.au/~tmccoy
MSN: (e-mail address removed)
ICQ: 160341067

 

[info_]

Hi,

I wonder if you just didn't forget to pull up your pin ?

SDIO <= 'H'; -- does it nicely.

Alternatively, your testbench could do
SDIO <= fromFPGA when (direction = '0') else 'H';

And my little trick :

toFPGA <= SDIO and SDIO; -- guess what for


Bert Cuzeau