Sistem Tasks in VHDL

Discussion in 'VHDL' started by kedarpapte@gmail.com, Mar 14, 2006.

  1. Guest

    Hi All,

    Do we have any System Tasks and Function in VHDL similar to Verilog
    like $stop, $finish

    which can be easily used to halt the simulation.

    Regards,
    Kedar
    , Mar 14, 2006
    #1
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