Situations in which 'else' or 'elsif' are unnecessary.

Discussion in 'VHDL' started by apalopohapa, Oct 20, 2009.

  1. apalopohapa

    apalopohapa

    Joined:
    Oct 20, 2009
    Messages:
    1
    Hello.

    Code:
    signal slv : std_logic_vector(1 downto 0);
    signal s1,s2 : std_logic;
    process()
    begin
      s1 <= '0';
      s2 <= '0';
    -----------------
    --
    -- Version with 'elsif'
    --
      if(slv = "00") then
        s1 = '1';
      elsif (slv = "10") then
        s2 = '1';
      end if;
    -----------------
    --
    -- Version without 'elsif'
    --
      if (slv = "00") then
        s1 <= '1';
      end if;
      if (slv = "10") then
        s2 <= '1';
      end if;
    -----------------
    end process;
    Any difference?
    Last edited: Oct 20, 2009
    apalopohapa, Oct 20, 2009
    #1
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