I came across the same problem. The reason is, the shift operators are only defined on bitvectors.
It isn't very hard to get around this though, as VHDL allows to overload functions - and operators can be seen as function calls.
To define a "sll" for std_logic_vector:
Code:
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift /= 0) then
for i in 1 to shift loop
ret := ret(val'high - 1 downto val'low) & '0';
end loop;
end if;
return ret;
end;
That one assumes the most significant bit is at the high index. Perhaps it isn't the prettiest way of doing this but it works;
Then to have a "sll" shift, depending on a variable: (yes this is silly but it's really needed! It's recognised as an idiom, at least by Xilinx)
Code:
function "sll"(val, shift : std_logic_vector) return std_logic_vector is
variable sel : std_logic_vector(4 downto 0) := shift(4 downto 0);
begin
case sel is
when "00000" => return (val sll 0);
when "00001" => return (val sll 1);
when "00010" => return (val sll 2);
-- etc
when others => return (val sll 31); -- "11111"
end case;
end;
Let me know if there's a better way of doing that.
One page, seems to suggest the expected functionality of
sla is really to shift the left-most (least significant bit) like
sra does with most significant bit. I don't really see why one would want that but it's trivial to adapt the code for such
sla operator.
(I can't post the URL as a new member, the forum seems to forbid to avoid spammers)