small FIFO?

[Matthias Alles]

Hello,

is there a smaller way to build a FIFO buffer in VHDL rather than using
a reading and a writing pointer? It should be possible to save the
reading pointer and the needed multiplexer when you read always from the
same position and ripple all data through the FIFO´s registers when
reading.

I need an as small implementation of a FIFO as possible but I need the
possibility to read and write simultaneously.

Can anyone help?

Thanks!

 

[Kai Harrekilde-Petersen]

Hello,

is there a smaller way to build a FIFO buffer in VHDL rather than
using a reading and a writing pointer? It should be possible to save
the reading pointer and the needed multiplexer when you read always
from the same position and ripple all data through the FIFO´s
registers when reading.

Definitely possible. However, it would burn more power than the
version with pointers.

Regards,


Kai

 

[Mike Treseler]

Definitely possible. However, it would burn more power than the
version with pointers.

Try it both ways and see.
The conventional design can make use of block ram.
Actually shifting the entire data pipeline
for each read would require registers instead.
You save a read counter, but the
write counter has to increment for a push
and decrement for a pop, so I'm not sure if
this is a "smaller way".

-- Mike Treseler

 

[Allan Herriman]

Try it both ways and see.
The conventional design can make use of block ram.
Actually shifting the entire data pipeline
for each read would require registers instead.
You save a read counter, but the
write counter has to increment for a push
and decrement for a pop, so I'm not sure if
this is a "smaller way".

If using Xilinx FPGAs, small FIFOs can be made using SRL shift
register primitives. The data trickles through the device, and only a
single counter / pointer is needed.

Regards,
Allan

 

[Matthias Alles]

If using Xilinx FPGAs, small FIFOs can be made using SRL shift
register primitives. The data trickles through the device, and only a
single counter / pointer is needed.

well, I´m not using FPGAs. I synthesized the smaller FIFO in a 0.13µm
technology and saved about 750 µm² with a FIFO with 29 entries and a
bitwidth of 6! That´s quite a lot I think.