Small problem in VHDL

Discussion in 'VHDL' started by zhe, Oct 5, 2008.

  1. zhe

    zhe

    Joined:
    Oct 5, 2008
    Messages:
    2
    Location:
    Chicago
    Hi friends,

    I'm new here and I meet a problem in VHDL, Could anybody please help me out?

    The module I need

    entity transfer is
    Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
    clk : in STD_LOGIC;
    output : out STD_LOGIC);
    end transfer;

    architecture Behavioral of transfer is
    begin

    here if input is "01",output should be a 2 clock cycle long pulse
    if input is "10", output should be a 4 clock cycle long pulse
    if input is "11", output should be a 6 clock cycle long pulse
    if input is "00", ouput remain low.

    need sychronized sythesisable circuit...
    input ONLY LAST ONE clock cycle

    end Behavioral;


    thanks!
    Last edited: Oct 5, 2008
    zhe, Oct 5, 2008
    #1
    1. Advertising

  2. zhe

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    A solution

    bHi
    First - I believe you learn more by doing your homework yourself - but nevermind :)

    The most traditional solution to this problem would be a statemachine with say 13 state (one idle and 2+4+6)

    This solution however based on a counter and variables.

    Code:
    --------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity pulse_generator1 is
    	Port ( input : in  STD_LOGIC_VECTOR (1 downto 0);
    				clk : in  STD_LOGIC;
    			output : out  STD_LOGIC);
    end pulse_generator1;
    
    architecture Behavioral of pulse_generator1 is
    
    begin
    
    	process( Clk)
    		type		states is (Idle, Pulse);
    		variable state: states := Idle;
    		variable counter: std_logic_vector( 2 downto 0);
    	begin
    		if rising_edge( clk) then
    			case state is
    				when Idle  =>
    						if input /= "00" then
    							state   := Pulse;
    							counter := input&'0'; -- Counter = input*2
    						end if;
    						output <= '0';
    				when Pulse =>
    						if counter > "001" then
    							counter := counter-1;
    						else
    							counter := "000";
    							state   := Idle;
    						end if;
    						output <= '1';
    			end case;
    		end if;
    	end process;
    
    end Behavioral;
    jeppe, Oct 5, 2008
    #2
    1. Advertising

  3. zhe

    zhe

    Joined:
    Oct 5, 2008
    Messages:
    2
    Location:
    Chicago
    Jeppe, thank you so much. actrually it is from a part of my project assignment. I don't know why but I just suddenly stuck at here for a few hours! I had thought about using counter but just cannot make it done. Maybe next time I should post my wrong code and you can point out my weakness in solving this kind of problem. Again, thanks for your self-explaining code.
    zhe, Oct 6, 2008
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    3
    Views:
    4,785
    walala
    Sep 18, 2003
  2. afd
    Replies:
    1
    Views:
    8,275
    Colin Paul Gloster
    Mar 23, 2007
  3. s_hlu

    a small vhdl problem

    s_hlu, Sep 24, 2008, in forum: VHDL
    Replies:
    1
    Views:
    466
    jeppe
    Sep 24, 2008
  4. omara007
    Replies:
    0
    Views:
    1,464
    omara007
    Jan 6, 2010
  5. Wing Chun
    Replies:
    7
    Views:
    799
Loading...

Share This Page