soustractor 12 bit vhdl ?

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Hi i am a new designer in vhdl and i want to write a vhdl code soustractor 12 bit. I want to do it in vhdl structural and at first i create an adder 12 bit in i want to use this adder to create soustractor 12 bit. My idea is i should use complement two for the second operand ( A - B = A + (-B)).

My question is : How can i create a structural vhdl code for soustractor 12 bit ?

Thank you very much !

Charko

NB: Sorry for my bad english!!
 
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I think i resolve this problem!

The vhdl code that i write to do that is :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity soustr12 is
Port ( a : in STD_LOGIC_VECTOR (11 downto 0);
b : in STD_LOGIC_VECTOR (11 downto 0);
s : out STD_LOGIC_VECTOR (11 downto 0));
end soustr12;

architecture structural of soustr12 is
component add12
port ( a : in std_logic_vector(11 downto 0 );
b: in std_logic_vector(11 downto 0) ;
s: out std_logic_vector(11 downto 0);
Cout: out std_logic);
end component ;
signal q : std_logic_vector( 11 downto 0 );


begin
q(11 downto 0) <= (not B(11 downto 0) ) + 1 ;
inst1 : add12 port map ( a(11 downto 0)=> a( 11 downto 0),
b( 11 downto 0)=> q(11 downto 0),
s( 11 downto 0)=> s (11 downto 0));
end structural;
----------------------------------------------------------------------------
I think that is rigth because the test bench give me a good result.
 
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If you're really looking for a structural solution, wouldn't you prefer to have a carry-in of 1 instead of adding 1 before-hand, and pass in 'not B'?
That could save a full adder for the incrementing.
 
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joris said:
If you're really looking for a structural solution, wouldn't you prefer to have a carry-in of 1 instead of adding 1 before-hand, and pass in 'not B'?
That could save a full adder for the incrementing.



hi Joris. ok i try it !!


Charko
 

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