Specify a VHDL file as vector waveform generator

Discussion in 'VHDL' started by Binary, Dec 13, 2005.

  1. Binary

    Binary Guest

    Hi,

    Can I specify a VHDL file as vector waveform generator in Quartus II
    instead draw a .vwf file, and how?

    And how to use a test bench entity to test my entity architecture?

    Thanks in advance.

    Binary Chen
    Binary, Dec 13, 2005
    #1
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  2. Binary wrote:

    > Can I specify a VHDL file as vector waveform generator in Quartus II
    > instead draw a .vwf file, and how?


    That would require a vhdl simulator.
    Quartus does not have one.

    > And how to use a test bench entity to test my entity architecture?


    Step one is to install a vhdl simulator
    and run some tutorial examples.
    A testbench is a vhdl text file.
    It includes a null entity and
    architecture processes
    to wiggle and watch the design instance.
    There is a testbench example here:
    http://home.comcast.net/~mike_treseler/


    -- Mike Treseler
    Mike Treseler, Dec 13, 2005
    #2
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  3. Binary

    Guest

    Several comments:
    1. You will find several verification answers and a good place to post
    interesting verification questions at
    http://verificationguild.com/ under MAIN
    2. In my books I have encouraged the use of transaction-based
    verification, which can be done in VHDL. I dislike the use of
    waveform stimulus files as a means to define directed tests. But ...
    3. The languages and technology has matured since the days of VHDL'93,
    and I now definitely prefer SystemVerilog with assertions as a means to
    verify designs. SystemVerilog provides the facilities to build a
    testbench that is transaction-based with constraints and can be
    coverage-driven. You can also top that with VMM (Verification
    Methodology Manual for SystemVerilog) to facilitate the design of the
    testbench environment. In any case, SystemVerilog can be used in
    mixed-mode with VHDL, along with assertions written in SVA (
    SystemVerilog assertions) or PSL,
    If I have a choice today to pick a language for verification, I would
    definitely pick SystemVerilog over VDHL. Of course, the tradeoff here
    is the cost of learning SV and tool cost if you do not have access to a
    SV simulator.
    --------------------------------------------------------------------------
    Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
    http://www.abv-sva.org/
    * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
    * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
    Edition, 2004, ISBN 0-9705394-6-0
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
    0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
    0-7923-8115
    ---------------------------------------------------------------------------
    , Dec 14, 2005
    #3
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