Specifying clock requirements for derived clocks...

Discussion in 'VHDL' started by Markus Jochim, Jul 24, 2007.

  1. Hello everybody,

    using Alteras Quartus-2 I have developed a very simple VDHL-design that
    controles several 7-Segment blocks. The design uses time-multiplexing in
    order to control the different 7-Segment blocks. It turned out that I
    get the best results (in terms of luminance) when I use a frequency of
    approx. 100 to 150 Hz for time-multiplexing and I developed a very
    simple prescaler that derives such a frequency on the basis of the 50
    MHz clock available on my board.

    When I synthesize the design, Quartus-2 complains that my design
    contains some gated or rippled clocks which may introduce clock skew
    which may in turn result in hold violations - and thats quite plain to me.

    Quartus-2 proposes the following:

    > Specify derived clock settings for
    > all nodes functioning as derived
    > clocks in the design.
    > The derived clock setting should
    > be derived from the clock settings
    > specified for the associated absolute
    > clock. Specifying derived clock settings
    > is especially important in cases in which
    > a ripple clock is acting as a clock divider.


    When I try to specify these settings I have to inform Quartus (Menu:
    "Assignment | Timing Analysis Settings | Classic Timing Analysis
    Settings | Individual Clocks | New | Based on | Derived Clock
    Requirements") about:

    1) the FlipFlop that serves as a derived clock
    2) the absolute clock on which the derived clock is based
    3) two values by which the absolute clock fmax must be multiplied / devided
    4) the duty cycle
    5) the offset from base absolute clock fmax (in ns)
    6) a clock phase shift in degrees with respect to the derived clock

    In the following I have listed two statements and a question. Since
    these statements are frankly spoken more or less only my assumptions on
    how reality is, I would be very helpful to me, if some expert could
    acknowledge (or contradict) the statements and would comment on the
    question:

    Statement 1:
    The values 5) and 6) must not be specified if - like in the 7-Segment
    example - the derived clock is an integral part of the design, since
    Quartus-2 will be able to caculate these values based on its own
    technology information about the FlipFlops in use, the line delays etc.

    Statement 2:
    After specifying the derived clock, the static timing analysis will
    consider that parts of my design are using a "slow clock" and the timing
    requirements which are posed on the associated combinational logic will
    be relaxed appropriately (100 Hz instead of 50 MHz).

    Question 3:
    For the described 7-Segement time multiplexing, a "high-quality clock"
    is not crucial. But what if I would intend to clock parts of a complex
    design using such a derived clock? I read that inside of an FPGA special
    care is taken to distribute the clock signal and to avoid clock skew
    ("clock tree" etc.). Is it nevertheless possible / good practice to use
    such a "hand made" prescaler to clock parts of a complex design or is it
    obligatory to use "special mechanisms" (PLLs or whatever) which may be
    available on some FPGAs (which I unfortunately do not use at the moment ;-))

    Thanks in advance to all those who assist with helpful information in
    this group

    Best regards
    Markus
    Markus Jochim, Jul 24, 2007
    #1
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  2. Markus Jochim

    devices Guest

    "Markus Jochim" <-due.de> wrote in message
    news:...
    > Hello everybody,
    >
    > using Alteras Quartus-2 I have developed a very simple VDHL-design that
    > controles several 7-Segment blocks. The design uses time-multiplexing in
    > order to control the different 7-Segment blocks. It turned out that I
    > get the best results (in terms of luminance) when I use a frequency of
    > approx. 100 to 150 Hz for time-multiplexing and I developed a very
    > simple prescaler that derives such a frequency on the basis of the 50
    > MHz clock available on my board.
    >
    > When I synthesize the design, Quartus-2 complains that my design
    > contains some gated or rippled clocks which may introduce clock skew
    > which may in turn result in hold violations - and thats quite plain to me.
    >
    > Quartus-2 proposes the following:
    >
    > > Specify derived clock settings for
    > > all nodes functioning as derived
    > > clocks in the design.
    > > The derived clock setting should
    > > be derived from the clock settings
    > > specified for the associated absolute
    > > clock. Specifying derived clock settings
    > > is especially important in cases in which
    > > a ripple clock is acting as a clock divider.

    >
    > When I try to specify these settings I have to inform Quartus (Menu:
    > "Assignment | Timing Analysis Settings | Classic Timing Analysis
    > Settings | Individual Clocks | New | Based on | Derived Clock
    > Requirements") about:
    >
    > 1) the FlipFlop that serves as a derived clock
    > 2) the absolute clock on which the derived clock is based
    > 3) two values by which the absolute clock fmax must be multiplied /

    devided
    > 4) the duty cycle
    > 5) the offset from base absolute clock fmax (in ns)
    > 6) a clock phase shift in degrees with respect to the derived clock
    >
    > In the following I have listed two statements and a question. Since
    > these statements are frankly spoken more or less only my assumptions on
    > how reality is, I would be very helpful to me, if some expert could
    > acknowledge (or contradict) the statements and would comment on the
    > question:
    >
    > Statement 1:
    > The values 5) and 6) must not be specified if - like in the 7-Segment
    > example - the derived clock is an integral part of the design, since
    > Quartus-2 will be able to caculate these values based on its own
    > technology information about the FlipFlops in use, the line delays etc.
    >
    > Statement 2:
    > After specifying the derived clock, the static timing analysis will
    > consider that parts of my design are using a "slow clock" and the timing
    > requirements which are posed on the associated combinational logic will
    > be relaxed appropriately (100 Hz instead of 50 MHz).
    >
    > Question 3:
    > For the described 7-Segement time multiplexing, a "high-quality clock"
    > is not crucial. But what if I would intend to clock parts of a complex
    > design using such a derived clock? I read that inside of an FPGA special
    > care is taken to distribute the clock signal and to avoid clock skew
    > ("clock tree" etc.). Is it nevertheless possible / good practice to use
    > such a "hand made" prescaler to clock parts of a complex design or is it
    > obligatory to use "special mechanisms" (PLLs or whatever) which may be
    > available on some FPGAs (which I unfortunately do not use at the moment

    ;-))
    >
    > Thanks in advance to all those who assist with helpful information in
    > this group
    >
    > Best regards
    > Markus


    I don't think your prescaler is a Derived Clock according to what
    the analyzer means. A PLL is a derived clock in this case. Don't
    base your clock on the "derived category" as your menu path shows.
    Find the node that sources your individual clock and set your
    specs in that DialogBox. It worked for me.
    devices, Jul 24, 2007
    #2
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