Speed grade of MAX7000S causes me problems...why??

[Matt Clement]

Hello

I recently designed a basic serial in parallel out IO board that used an
Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as
expected and everything was fine. I found that I could purchase the
7128slc84-15 chip for about half the price so I did, and now my same setup
doesnt work. I recompiled the VHDL for the 15 speed grade chip without any
problems and yet it does not run my program correctly. I have loaded a
small test program on the 15 chip and it works fine and does what it should.
My code is using an external clock to run the state machine so I dont
understand why it makes any difference whether I use a -10 or a -15..

What should I look for to make this 15 grade chip run my code without
problems?? Does a jump in speed make that big of a difference?

 

[Mike Treseler]

I found that I could purchase the
7128slc84-15 chip for about half the price so I did, and now my same setup
doesnt work. I recompiled the VHDL for the 15 speed grade chip without any
problems and yet it does not run my program correctly.

Run static timing on Quartus.

What should I look for to make this 15 grade chip run my code without
problems?? Does a jump in speed make that big of a difference?

10ns to 15ns is a drop in speed, not a jump.
Yes, this can break a design.
If you have extra flops, you might be able
to pipeline the data path to increase Fmax
and make it work again.

If the design is not synchronous, make it so.

-- Mike Treseler

 

[Matt Clement]

Hey Mike
Thanks for the reply.

I was under the assumption that the -15 chip was faster than the -10. I
will check the datasheet to prove myself wrong..haha.
The design is synchronous using a state machine. Here is the bulk of the
code.

Thanks

-------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


ENTITY CLONE34 IS
PORT
(clk : IN BIT;
SEL : IN BIT_VECTOR(7 DOWNTO 0);
ADD : IN BIT_VECTOR(5 DOWNTO 0);
DAT : INOUT BIT_VECTOR(1 DOWNTO 0);
LED1 : OUT BIT_VECTOR(31 DOWNTO 0));

END CLONE34;

ARCHITECTURE ONE OF CLONE34 IS
TYPE STATE_TYPE IS
(IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34);
SIGNAL STATE: STATE_TYPE;

BEGIN

PROCESS (clk, ADD)
VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0);
BEGIN

IF (clk'EVENT AND clk = '1')THEN

DAT(0)<='0';
CASE STATE IS
WHEN IDLE =>

IF ADD = SEL(7 DOWNTO 2) THEN
DATA(35):=SEL(1);
STATE<=S0;


ELSE
STATE<=IDLE;

END IF;

WHEN S0 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(34):=SEL(1);
STATE <= S1;
ELSE
STATE<=IDLE;
END IF;


WHEN S1 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(33):=SEL(1);

STATE <= S2;
ELSE
STATE<=IDLE;
END IF;


WHEN S2 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(32):=SEL(1);

STATE <= S3;
ELSE
STATE<=IDLE;
END IF;
WHEN S3 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(31):=SEL(1);

STATE <= S4;
ELSE
STATE<=IDLE;
END IF;
WHEN S4 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(30):=SEL(1);

STATE <= S5;
ELSE
STATE<=IDLE;
END IF;
WHEN S5 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(29):=SEL(1);

STATE <= S6;
ELSE
STATE<=IDLE;
END IF;

WHEN S6 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(28):=SEL(1);

STATE <= S7;
ELSE
STATE<=IDLE;
END IF;

WHEN S7 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(27):=SEL(1);

STATE <= S8;
ELSE
STATE<=IDLE;
END IF;
WHEN S8 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(26):=SEL(1);

STATE <= S9;
ELSE
STATE<=IDLE;
END IF;

WHEN S9 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(25):=SEL(1);

STATE <= S10;
ELSE
STATE<=IDLE;
END IF;
WHEN S10 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(24):=SEL(1);

STATE <= S11;
ELSE
STATE<=IDLE;
END IF;
WHEN S11 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(23):=SEL(1);

STATE <= S12;
ELSE
STATE<=IDLE;
END IF;
WHEN S12 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(22):=SEL(1);

STATE <= S13;
ELSE
STATE<=IDLE;
END IF;
WHEN S13 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(21):=SEL(1);

STATE <= S14;
ELSE
STATE<=IDLE;
END IF;
WHEN S14 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(20):=SEL(1);

STATE <= S15;
ELSE
STATE<=IDLE;
END IF;
WHEN S15 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(19):=SEL(1);

STATE <= S16;
ELSE
STATE<=IDLE;
END IF;
WHEN S16 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(18):=SEL(1);

STATE <= S17;
ELSE
STATE<=IDLE;
END IF;
WHEN S17 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(17):=SEL(1);

STATE <= S18;
ELSE
STATE<=IDLE;
END IF;

WHEN S18 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(16):=SEL(1);

STATE <= S19;
ELSE
STATE<=IDLE;
END IF;
WHEN S19 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(15):=SEL(1);

STATE <= S20;
ELSE
STATE<=IDLE;
END IF;

WHEN S20 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(14):=SEL(1);

STATE <= S21;
ELSE
STATE<=IDLE;
END IF;


WHEN S21 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(13):=SEL(1);

STATE <= S22;
ELSE
STATE<=IDLE;
END IF;



WHEN S22 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(12):=SEL(1);

STATE <= S23;
ELSE
STATE<=IDLE;
END IF;


WHEN S23 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(11):=SEL(1);

STATE <= S24;
ELSE
STATE<=IDLE;
END IF;


WHEN S24 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(10):=SEL(1);

STATE <= S25;
ELSE
STATE<=IDLE;
END IF;


WHEN S25 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(9):=SEL(1);

STATE <= S26;
ELSE
STATE<=IDLE;
END IF;


WHEN S26 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(8):=SEL(1);

STATE <= S27;
ELSE
STATE<=IDLE;
END IF;



WHEN S27 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(7):=SEL(1);

STATE <= S28;
ELSE
STATE<=IDLE;
END IF;



WHEN S28 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(6):=SEL(1);

STATE <= S29;
ELSE
STATE<=IDLE;
END IF;


WHEN S29 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(5):=SEL(1);

STATE <= S30;
ELSE
STATE<=IDLE;
END IF;



WHEN S30 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(4):=SEL(1);

STATE <= S31;
ELSE
STATE<=IDLE;
END IF;


WHEN S31 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(3):=SEL(1);

STATE <= S32;
ELSE
STATE<=IDLE;
END IF;


WHEN S32 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(2):=SEL(1);

STATE <= S33;
ELSE
STATE<=IDLE;
END IF;


WHEN S33 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(1):=SEL(1);

STATE <= S34;

ELSE
STATE<=IDLE;
END IF;

WHEN S34 =>
DAT(0)<='1';
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(0):=SEL(1);

STATE <= IDLE;

--THIS IS WHERE WE WOULD DO OUR PARITY CHECK FOR INCOMING DATA
--DATA(35,34,33,32) = PARITY4,3,2,1
--IF PARITY1=BLAH BLAH AND
-- PARITY2=BLAH BLAH AND
-- PARITY3=BLAH BLAH AND
-- PARITY4=BLAH BLAH THEN

LED1(31 downto 0)<=DATA(31 downto 0);

--END IF;


ELSE
STATE<=IDLE;


END IF;
END CASE;
ELSE


END IF;
END PROCESS;
END ONE;

 

[ALuPin]

Hi Matt,

are you using a set of additional input and output registers?
They help to relax timing if that is relevant.


Rgds
André

 

[Matt Clement]

Hello Andre
I am not sure what you are asking me here. I sample the input into a temp
register and then drive the outputs with it once its done being sent. How
can I tell if I am using input/output registers?
Thanks
Matt


Hi Matt,

are you using a set of additional input and output registers?
They help to relax timing if that is relevant.


Rgds
André

 

[ALuPin]

Hi Matt,

if do not connect the signal from the MAX7000S input pin directly to
your VHDL module
you showed us, but instead you connect the input pin to a INPUT
register and then
connect the output of that INPUT register to your VHDL module,
you can be sure that the timing is relaxed concerning SETUP, HOLD
timings (as it
was discussed in the FPGA forum). Static timing analysis does help to
analyze
these timings.


Input Pin ---> INPUT register ---> synchronous logic ---> OUTPUT
register --> Output Pin

Rgds
André