SPI confusion

Discussion in 'VHDL' started by Niv, Sep 12, 2006.

  1. Niv

    Niv Guest

    I have to interface several DACs, ADCs and temp sensors (all different
    mnfrs of course) to an FPGA.
    Now, the data sheets all say they are SPI compatible.
    All seem to have a serial clock and chip select input.
    The DACs have serial data input,
    the ADCs have serial data output,
    the temp sensor has a single data I/O pin!

    Now the SPI spec seems to sort of agree (not with single I/O pin
    though).
    I need to write some VHDL that'll handle all the above, so I have a
    common module,
    in, out & I/O controlled by generics probably (as well as max clock
    speed).

    The VHDL block will be the master, controlled via our in-house common
    bus structure from
    a remote(ish) processor

    Anyone point me at some SPI clarification please?

    (Or I could be greedy & ask for pre-written example to start me off).

    Regards, Niv.
     
    Niv, Sep 12, 2006
    #1
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  2. Paul Uiterlinden, Sep 12, 2006
    #2
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  3. Niv wrote:
    > I have to interface several DACs, ADCs and temp sensors (all different
    > mnfrs of course) to an FPGA.
    > Now, the data sheets all say they are SPI compatible.
    > All seem to have a serial clock and chip select input.
    > The DACs have serial data input,
    > the ADCs have serial data output,
    > the temp sensor has a single data I/O pin!
    >
    > Now the SPI spec seems to sort of agree (not with single I/O pin
    > though).
    > I need to write some VHDL that'll handle all the above, so I have a
    > common module,
    > in, out & I/O controlled by generics probably (as well as max clock
    > speed).
    >
    > The VHDL block will be the master, controlled via our in-house common
    > bus structure from
    > a remote(ish) processor
    >
    > Anyone point me at some SPI clarification please?
    >
    > (Or I could be greedy & ask for pre-written example to start me off).
    >
    > Regards, Niv.
    >

    The temp sensor isn't a Dallas "One Wire" device, by any chance?
    1W and SPI are two very different beasts.
     
    David R Brooks, Sep 13, 2006
    #3
  4. Niv

    Niv Guest

    David R Brooks wrote:
    > Niv wrote:
    > > I have to interface several DACs, ADCs and temp sensors (all different
    > > mnfrs of course) to an FPGA.
    > > Now, the data sheets all say they are SPI compatible.
    > > All seem to have a serial clock and chip select input.
    > > The DACs have serial data input,
    > > the ADCs have serial data output,
    > > the temp sensor has a single data I/O pin!
    > >
    > > Now the SPI spec seems to sort of agree (not with single I/O pin
    > > though).
    > > I need to write some VHDL that'll handle all the above, so I have a
    > > common module,
    > > in, out & I/O controlled by generics probably (as well as max clock
    > > speed).
    > >
    > > The VHDL block will be the master, controlled via our in-house common
    > > bus structure from
    > > a remote(ish) processor
    > >
    > > Anyone point me at some SPI clarification please?
    > >
    > > (Or I could be greedy & ask for pre-written example to start me off).
    > >
    > > Regards, Niv.
    > >

    > The temp sensor isn't a Dallas "One Wire" device, by any chance?
    > 1W and SPI are two very different beasts.


    No, it's an LM70, supposedly "SPI" but has a single I/O pin along with
    clock & cs pins.
    It switches from output to input after 16 clocks if cs is still active.
    Think I'll just not use that feature as it powers up in "normal" mode.

    Niv.
     
    Niv, Sep 13, 2006
    #4
  5. Niv

    devices Guest

    I guess that "SPI compatible" only refers to
    "One master device - to - One slave device" topology.
    Chances are that they were not meant to be used in a chain

    "Niv" <> wrote in message
    news:...
    >
    > David R Brooks wrote:
    > > Niv wrote:
    > > > I have to interface several DACs, ADCs and temp sensors (all different
    > > > mnfrs of course) to an FPGA.
    > > > Now, the data sheets all say they are SPI compatible.
    > > > All seem to have a serial clock and chip select input.
    > > > The DACs have serial data input,
    > > > the ADCs have serial data output,
    > > > the temp sensor has a single data I/O pin!
    > > >
    > > > Now the SPI spec seems to sort of agree (not with single I/O pin
    > > > though).
    > > > I need to write some VHDL that'll handle all the above, so I have a
    > > > common module,
    > > > in, out & I/O controlled by generics probably (as well as max clock
    > > > speed).
    > > >
    > > > The VHDL block will be the master, controlled via our in-house common
    > > > bus structure from
    > > > a remote(ish) processor
    > > >
    > > > Anyone point me at some SPI clarification please?
    > > >
    > > > (Or I could be greedy & ask for pre-written example to start me off).
    > > >
    > > > Regards, Niv.
    > > >

    > > The temp sensor isn't a Dallas "One Wire" device, by any chance?
    > > 1W and SPI are two very different beasts.

    >
    > No, it's an LM70, supposedly "SPI" but has a single I/O pin along with
    > clock & cs pins.
    > It switches from output to input after 16 clocks if cs is still active.
    > Think I'll just not use that feature as it powers up in "normal" mode.
    >
    > Niv.
    >
     
    devices, Sep 13, 2006
    #5
  6. Niv

    Dal Guest

    Downalod the Motorola (Freescale) 68HC11 data sheet and see the
    Synchronous Peripheral Interface section.

    Darrin

    Niv wrote:
    > I have to interface several DACs, ADCs and temp sensors (all different
    > mnfrs of course) to an FPGA.
    > Now, the data sheets all say they are SPI compatible.
    > All seem to have a serial clock and chip select input.
    > The DACs have serial data input,
    > the ADCs have serial data output,
    > the temp sensor has a single data I/O pin!
    >
    > Now the SPI spec seems to sort of agree (not with single I/O pin
    > though).
    > I need to write some VHDL that'll handle all the above, so I have a
    > common module,
    > in, out & I/O controlled by generics probably (as well as max clock
    > speed).
    >
    > The VHDL block will be the master, controlled via our in-house common
    > bus structure from
    > a remote(ish) processor
    >
    > Anyone point me at some SPI clarification please?
    >
    > (Or I could be greedy & ask for pre-written example to start me off).
    >
    > Regards, Niv.
     
    Dal, Sep 14, 2006
    #6
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