split matrices

Discussion in 'VHDL' started by mkokelma, Oct 21, 2004.

  1. mkokelma

    mkokelma Guest

    Hello,

    I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.

    I want to split a matrix.
    For example
    I have a port "in" with 6 rows, 110011.

    I want to split it to 2 ports
    The ports are: "en" with 2 rows and "opsel" with 4 rows.

    The result must: en=11 and opsel=0011

    How can I do this.
    I have already tested:
    en<=in (5 DOWNMTO 4);
    opsel<= in (3 DOWNTO 0);

    It didn't work in autologic II.

    After synthesis the es an error with

    Type mismatch ... netlist failed.

    What can I do.

    Thanks
    Martin
     
    mkokelma, Oct 21, 2004
    #1
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  2. mkokelma a écrit:
    > Hello,
    >
    > I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.
    >
    > I want to split a matrix.
    > For example
    > I have a port "in" with 6 rows, 110011.


    'in' is a VHDL keyword, you can not use it to name a port, signal...


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Oct 21, 2004
    #2
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  3. mkokelma

    mkokelma Guest

    Nicolas Matringe schrieb:
    > mkokelma a écrit:
    >
    >> Hello,
    >>
    >> I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.
    >>
    >> I want to split a matrix.
    >> For example
    >> I have a port "in" with 6 rows, 110011.

    >
    >
    > 'in' is a VHDL keyword, you can not use it to name a port, signal...
    >
    >

    Oh sorry. I have meant "ein"

    Martin
     
    mkokelma, Oct 21, 2004
    #3
  4. mkokelma

    mkokelma Guest

    mkokelma schrieb:
    > Hello,
    >
    > I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.
    >
    > I want to split a matrix.
    > For example
    > I have a port "in" with 6 rows, 110011.
    >
    > I want to split it to 2 ports
    > The ports are: "en" with 2 rows and "opsel" with 4 rows.
    >
    > The result must: en=11 and opsel=0011
    >
    > How can I do this.
    > I have already tested:
    > en<=in (5 DOWNMTO 4);
    > opsel<= in (3 DOWNTO 0);
    >
    > It didn't work in autologic II.
    >
    > After synthesis the es an error with
    >
    > Type mismatch ... netlist failed.
    >
    > What can I do.
    >
    > Thanks
    > Martin
    >


    Type mismatch in assignment to netlist ...
    is the error I get. What is wrong?

    Martin
     
    mkokelma, Oct 21, 2004
    #4
  5. mkokelma

    rickman Guest

    mkokelma wrote:
    >
    > mkokelma schrieb:
    > > Hello,
    > >
    > > I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.
    > >
    > > I want to split a matrix.
    > > For example
    > > I have a port "in" with 6 rows, 110011.
    > >
    > > I want to split it to 2 ports
    > > The ports are: "en" with 2 rows and "opsel" with 4 rows.
    > >
    > > The result must: en=11 and opsel=0011
    > >
    > > How can I do this.
    > > I have already tested:
    > > en<=in (5 DOWNMTO 4);
    > > opsel<= in (3 DOWNTO 0);
    > >
    > > It didn't work in autologic II.
    > >
    > > After synthesis the es an error with
    > >
    > > Type mismatch ... netlist failed.
    > >
    > > What can I do.
    > >
    > > Thanks
    > > Martin
    > >

    >
    > Type mismatch in assignment to netlist ...
    > is the error I get. What is wrong?


    How did you define ein and en? Are they compatible types?

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 21, 2004
    #5
  6. mkokelma

    mkokelma Guest

    rickman schrieb:
    > mkokelma wrote:
    >
    >>mkokelma schrieb:
    >>
    >>>Hello,
    >>>
    >>>I'm a beginner in vhdl. I use Mentor Graphics for programming VHDL.
    >>>
    >>>I want to split a matrix.
    >>>For example
    >>>I have a port "in" with 6 rows, 110011.
    >>>
    >>>I want to split it to 2 ports
    >>>The ports are: "en" with 2 rows and "opsel" with 4 rows.
    >>>
    >>>The result must: en=11 and opsel=0011
    >>>
    >>>How can I do this.
    >>>I have already tested:
    >>>en<=in (5 DOWNMTO 4);
    >>>opsel<= in (3 DOWNTO 0);
    >>>
    >>>It didn't work in autologic II.
    >>>
    >>>After synthesis the es an error with
    >>>
    >>>Type mismatch ... netlist failed.
    >>>
    >>>What can I do.
    >>>
    >>>Thanks
    >>>Martin
    >>>

    >>
    >>Type mismatch in assignment to netlist ...
    >>is the error I get. What is wrong?

    >
    >
    > How did you define ein and en? Are they compatible types?
    >

    --Dekoder zur Auswahl der jeweiligen Funktionsbloecke von der ALU

    This is the hole source from vhdl. This doesn't work in autologic II.
    The comments are in german.

    Martin


    LIBRARY IEEE, ARITHMETIC;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE ARITHMETIC.STD_LOGIC_ARITH.ALL;

    ENTITY decoder IS
    PORT (ein: IN STD_LOGIC_VECTOR (5 DOWNTO 0); --Eingangssignal
    waehlt Funktion aus
    en: OUT STD_LOGIC_VECTOR (1 DOWNTO 0); --enable-Signal zur Auswahl
    des Funktionblocks
    opsel: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

    END decoder;

    ARCHITECTURE behav OF decoder IS
    SIGNAL fktsel: STD_LOGIC_VECTOR (1 DOWNTO 0);


    BEGIN
    fktsel <= ein (5 DOWNTO 4); --Funktionsauswahl der ALU
    opsel <= ein (3 DOWNTO 0); --Operationsauswahl im
    Funktionsblock selbst

    --Auswahl der Funktion von der ALU
    p1: PROCESS (fktsel)
    BEGIN
    CASE fktsel IS
    WHEN "00" =>en<= "00"; --Auswahl der Funktion ADDER
    WHEN "01" =>en<= "01"; --Auswahl der Funktion 2er-Komplement
    WHEN "10" =>en<= "10"; --Auswahl der Funktion ROTATION
    WHEN "11" =>en<= "11"; --Auswahl der Funktion LOGIK
    WHEN OTHERS =>en<= "--";
    END CASE;
    END PROCESS p1;
    END behav;
     
    mkokelma, Oct 22, 2004
    #6
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