'stable operator

Discussion in 'VHDL' started by sridar, Feb 10, 2010.

  1. sridar

    sridar

    Joined:
    Jun 5, 2007
    Messages:
    51
    Can I use 'stable operator in VHDL to monitor the change of signal level without using it as clock signal.

    Signal a : std_logic;

    begin

    process ()

    If rising_edge (clk) then

    if (not a'stable) then

    Dout <= Din;

    end if;

    end if;

    But this gives me error in xilinx ISE and I had to use the stable operator as clock signal like,

    if (not a'stable and a='1')

    any guidelines of how to use 'stable operator
     
    sridar, Feb 10, 2010
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. clintonG

    Is 2.0 AdRotator Stable?

    clintonG, Mar 27, 2006, in forum: ASP .Net
    Replies:
    1
    Views:
    341
    clintonG
    Mar 27, 2006
  2. metfan

    Is JDK5.0 stable enough?

    metfan, Nov 23, 2004, in forum: Java
    Replies:
    6
    Views:
    731
    Oscar kind
    Nov 24, 2004
  3. Katerina McLean
    Replies:
    2
    Views:
    763
    Jacob
    Dec 13, 2004
  4. Rico
    Replies:
    8
    Views:
    2,776
    Alin Sinpalean via JavaKB.com
    Dec 31, 2004
  5. Bruce Lee

    How stable is 1.5?

    Bruce Lee, Oct 30, 2005, in forum: Java
    Replies:
    5
    Views:
    1,422
    Bruce Lee
    Nov 8, 2005
Loading...

Share This Page