Standardized internal module bus

Discussion in 'VHDL' started by Richo, Dec 28, 2006.

  1. Richo

    Richo Guest

    Hi All,

    I'm trying to have a standardized internal bus for reading & writing
    module registers. The external bus is more or less a standard SRAM type
    bus (CLK, NCE, RDNWR, ADDRESS, DATA + NRESET), and I can implement the
    read/write for a simple register ok. However, what I'm trying to do is
    have a single data bus shared by all modules and have each module
    implement their own registers (the code is below). This works fine
    until I have more than one module on the bus - as soon as I do this, I
    get an error (Xilinx ISE) of "Multi-source in Unit <Framework> on
    signal <DATA_BUS_IN<15>>". I realize that both modules are connecting
    to the same bus, but due to the chip selects, only one module is ever
    driving data onto the bus at any given time. Obviously, I can just have
    a huge bus (16 bits for every module) and run them through a
    multiplexor, but this seems to be a very innefficient use of resources.
    Any ideas how I can use a single bus to implement the register
    interface for all modules? I've cut and paste the code below.

    Thanks,

    Glenn.

    ------------------------------------

    Inside module:

    process (CLK) is
    begin
    if CLK'event and CLK = '1' then
    if (NRESET = '0') then
    -- Initialize the registers
    resetRegisters(kRegMax, registers, reg_init);
    else
    -- Do the register read/write
    doReadWrite(kRegMax, registers, NCS, RDNWR, DATA_BUS_IN,
    DATA_BUS_OUT, ADDRESS);
    end if;
    end if;
    end process;


    ------------------------------------

    Procedure definitions:

    -- Procedure to reset registers
    procedure resetRegisters(maxreg : in positive;
    signal registers : out data_register(maxreg
    downto 0);
    reg_init : in data_register(maxreg
    downto 0)
    ) is
    begin
    -- Loop through the registers and assign the initialization value
    for i in 0 to maxreg loop
    -- Assign register
    registers(i) <= reg_init(i);
    end loop;
    end resetRegisters;

    procedure doReadWrite(maxreg : in positive;
    signal registers : inout
    data_register(maxreg downto 0);
    NCS, RDNWR : in std_logic;
    signal DATA_BUS_IN : in std_logic_vector(15
    downto 0);
    signal DATA_BUS_OUT : out std_logic_vector(15
    downto 0);
    signal address : in STD_LOGIC_VECTOR (3
    downto 0)
    ) is

    begin
    if (NCS = '0') then
    -- Determine the address offset
    if (RDNWR = '1') then
    -- Read cycle, output the data
    DATA_BUS_OUT <= registers(CONV_INTEGER(address));
    else
    -- Write cycle, write the data to the register
    registers(CONV_INTEGER(address)) <= DATA_BUS_IN;
    end if;
    --else
    -- Don't output data onto the bus
    DATA_BUS_OUT <= "ZZZZZZZZZZZZZZZZ";
    end if;
    end doReadWrite;
     
    Richo, Dec 28, 2006
    #1
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  2. "Richo" <> writes:

    > Obviously, I can just have
    > a huge bus (16 bits for every module) and run them through a
    > multiplexor, but this seems to be a very innefficient use of resources.
    > Any ideas how I can use a single bus to implement the register


    This is how it's normally done. Check if your device supports internal
    tri-state signals.

    Regards,
    -- Marcus
     
    Marcus Harnisch, Dec 28, 2006
    #2
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  3. Richo

    Richo Guest

    Hi Marcus,

    Thanks for the suggestion - it wasn't actually the problem, but it
    turns out I was driving onto the bus in two different modules. Anyway,
    the code I pasted above works fine, thanks :)

    Glenn.

    On Dec 28, 9:26 pm, Marcus Harnisch <> wrote:
    > "Richo" <> writes:
    > > Obviously, I can just have
    > > a huge bus (16 bits for every module) and run them through a
    > > multiplexor, but this seems to be a very innefficient use of resources.
    > > Any ideas how I can use a single bus to implement the registerThis is how it's normally done. Check if your device supports internal

    > tri-state signals.
    >
    > Regards,
    > -- Marcus
     
    Richo, Dec 28, 2006
    #3
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