state change

[Urban Stadler]

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

thanks
urban

 

[Urban Stadler]

thanks for the answer but is there a better solution?
my signals are not syncron to the clock.
i need something that works 100% without glitches.

i tried the "transition" but that gives me an error?
is that not synthesizeable?

 

[Ken Smith]

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

If you want it to be psudo-edge operated:

Lets say your input signal is called ResetOnRise.

In the process section that makes the counter count, you assign another
signal like this:

DelayedResetOnRise <= ResetOnRise;

Now if you combine them like this:

(ResetOnRise AND NOT DelayedResetOnRise)

you have the needed combination to zero the counter.

WARN:

You can creat timing glitches if ResetOnRise is not timed to same clock as
the DelayedResetOnRise. If thats the case you need a tad more logic to
get the job done.

 

[Mike Treseler]

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

You can convert a rising input into a synchronous
strobe with a flop to watch the previous value
and gating for last_low AND now_high.

Here's a related example, counting rising edges.
-- Mike Treseler

-- rising edge counter example Tue Aug 31 22:58:37 2004 Mike Treseler
library ieee;
use ieee.std_logic_1164.all;
package edge_package is
procedure ck_rising(watch : in std_ulogic;
last : inout boolean;
strobe : out boolean);
end package edge_package;
package body edge_package is
procedure ck_rising(watch : in std_ulogic;
last : inout boolean;
strobe : out boolean)
is begin
strobe := watch = '1' and last;
last := watch = '0'; -- assign variable for next time
end procedure ck_rising;
end package body edge_package;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.edge_package.ck_rising;
entity edge_count is
port (clk : in std_ulogic;
rst : in std_ulogic;
edge : in std_ulogic;
count: out unsigned(15 downto 0)
);
end entity edge_count;

architecture synth of edge_count is
begin -- architecture synth
process (clk, rst) is
variable last_v : boolean;
variable strobe_v : boolean;
variable count_v : unsigned(count'range);
begin -- process
clked:if rst = '1' then
count <= (others => '0');
elsif rising_edge(clk) then
ck_rising(watch => edge,
last => last_v,
strobe => strobe_v);
if strobe_v then
count_v := count_v+1;
end if;
count <= count_v;
end if clked;
end process;
end architecture synth;

 

[ALuPin]

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

thanks
urban

Hi,

one possibility could be that you use an oversampling clock "clock_oversample"
and look for logic level change.

"If you have the time" you can of course also use two flipflops clocked with
the original clock

process(clock)
begin
if rising_edge(clock) then
sample_1 <= signal_to_sample;
sample_2 <= sample_1;
end if;
end process;

Then compare the content of the registers.