state machine sync process

Discussion in 'VHDL' started by Andrei Bejenari, Mar 9, 2005.

  1. Hello,

    In a Xilinx manual there is the above example of a state machine. My
    question is why there is a separate process SYNC_PROC to change the
    machine's state. Can't it be done in a single process and using a single
    signal for the current state?

    entity enum is
    port (
    CLOCK, RESET : in STD_LOGIC;
    A, B, C, D, E : in BOOLEAN;
    SINGLE, MULTI, CONTIG : out STD_LOGIC
    );
    end enum;

    architecture BEHV of enum is
    type STATE_TYPE is (S1, S2, S3, S4, S5, S6, S7);
    signal CS, NS: STATE_TYPE;
    begin
    SYNC_PROC: process (CLOCK, RESET)
    begin
    if (RESET='1') then
    CS <= S1;
    elsif (CLOCK'event and CLOCK = '1') then
    CS <= NS;
    end if;
    end process; --End SYNC_PROC
    COMB_PROC: process (CS, A, B, C, D, E)
    begin
    case CS is
    when S1 =>
    MULTI <= '0';
    CONTIG <= '0';
    SINGLE <= '0';
    ..
    ..
    ..

    Thanks,

    4ndre1.
    Andrei Bejenari, Mar 9, 2005
    #1
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  2. Andrei Bejenari wrote:

    > In a Xilinx manual there is the above example of a state machine. My

    ^^^^^^^
    sorry, the example is below ;)

    >
    > entity enum is
    > port (
    > CLOCK, RESET : in STD_LOGIC;
    > A, B, C, D, E : in BOOLEAN;
    > SINGLE, MULTI, CONTIG : out STD_LOGIC
    > );
    > end enum;
    >
    > architecture BEHV of enum is
    > type STATE_TYPE is (S1, S2, S3, S4, S5, S6, S7);
    > signal CS, NS: STATE_TYPE;
    > begin
    > SYNC_PROC: process (CLOCK, RESET)
    > begin
    > if (RESET='1') then
    > CS <= S1;
    > elsif (CLOCK'event and CLOCK = '1') then
    > CS <= NS;
    > end if;
    > end process; --End SYNC_PROC
    > COMB_PROC: process (CS, A, B, C, D, E)
    > begin
    > case CS is
    > when S1 =>
    > MULTI <= '0';
    > CONTIG <= '0';
    > SINGLE <= '0';
    > .
    > .
    > .
    >


    Thanks,

    4ndre1.
    Andrei Bejenari, Mar 9, 2005
    #2
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  3. Andrei Bejenari

    ALuPin Guest

    Hi,

    of course you can use one single clocked process.

    The advantage of using two separated processes - one for the register
    transfers and one for the combinational logic -
    is that you can generate signals which are combinational. If you use
    only one
    clocked process you will generate registered output signals out of the
    state machine.

    One disadvantage of using two processes is that you have to take care
    about the sensitivity list of the combinational process.

    Hope this helps.

    Rgds
    ALuPin, Mar 9, 2005
    #3
  4. Andrei Bejenari

    Neo Guest

    No, it can be done both ways giving the same implementattion. But it
    helps to have it seperate if the state determining logic is quite
    elaborate.
    Neo, Mar 10, 2005
    #4
  5. Neo wrote:
    > No, it can be done both ways giving the same implementattion. But it
    > helps to have it seperate if the state determining logic is quite
    > elaborate.


    An alternative is to collect that elaborate logic
    into well-named procedures and functions in order
    to unclutter your state case statement.
    Put the declarations between the IS and BEGIN
    of the clocked process. Doesn't cost a thing
    in utilization and it makes it easier to
    try out logic revisions.


    -- Mike Treseler
    Mike Treseler, Mar 10, 2005
    #5
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