State machine transition on internal signals -- is it legal?

Discussion in 'VHDL' started by Divyang M, May 15, 2005.

  1. Divyang M

    Divyang M Guest

    Hi,

    I am coding a state machine and have the transition from one state to
    the next (or back to the same state) conditional on an internal signal.
    The internal signal is essentially a counter. Is this OK to do and is
    it synthesizable? Any forseen problems with it?

    Here is a snippet of the state machine (one process type).
    process(clk, rst) -- sensitivity list
    "newline" is an INPUT port
    "mydelay", "vert", and "horiz" are SIGNALs

    when WAIT_16 =>
    if newline = '1' then
    mydelay <= mydelay + 1;
    end if;

    if mydelay < 16 then
    next_state <= WAIT_16;
    else
    next_state <= DO_PROCESSING;
    end if;

    when DO_PROCESSING =>
    if horiz < 640 then
    horiz <= horiz + 1;
    next_state <= DO_PROCESSING;
    else
    next_state <= WAIT_FOR_NEWLINE;
    end if;

    when WAIT_FOR_NEWLINE =>
    if newline = '1' then
    if vert < 240 then
    vert <= vert + 1;
    else
    vert <= 0;
    end if;
    horiz <= 0;
    next_state <= DO_PROCESSING;
    else
    next_state <= WAIT_FOR_NEWLINE;
    end if;

    end case;

    Thanks,
    Divyang M
    Divyang M, May 15, 2005
    #1
    1. Advertising

  2. Divyang M

    Jerzy Gbur Guest

    Divyang M wrote:
    > Hi,
    >
    > I am coding a state machine and have the transition from one state to
    > the next (or back to the same state) conditional on an internal signal.
    > The internal signal is essentially a counter. Is this OK to do and is
    > it synthesizable? Any forseen problems with it?
    >
    > Here is a snippet of the state machine (one process type).
    > process(clk, rst) -- sensitivity list
    > "newline" is an INPUT port
    > "mydelay", "vert", and "horiz" are SIGNALs
    >
    > when WAIT_16 =>
    > if newline = '1' then
    > mydelay <= mydelay + 1;
    > end if;
    >
    > if mydelay < 16 then
    > next_state <= WAIT_16;
    > else
    > next_state <= DO_PROCESSING;
    > end if;
    >
    > when DO_PROCESSING =>
    > if horiz < 640 then
    > horiz <= horiz + 1;
    > next_state <= DO_PROCESSING;
    > else
    > next_state <= WAIT_FOR_NEWLINE;
    > end if;
    >
    > when WAIT_FOR_NEWLINE =>
    > if newline = '1' then
    > if vert < 240 then
    > vert <= vert + 1;
    > else
    > vert <= 0;
    > end if;
    > horiz <= 0;
    > next_state <= DO_PROCESSING;
    > else
    > next_state <= WAIT_FOR_NEWLINE;
    > end if;
    >
    > end case;


    On the first glance it should work.

    regards

    Jerzy Gbur
    Jerzy Gbur, May 15, 2005
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Fred Bartoli

    Writing state machine output signals.

    Fred Bartoli, Dec 18, 2004, in forum: VHDL
    Replies:
    1
    Views:
    483
    Mike Treseler
    Dec 18, 2004
  2. Divyang M
    Replies:
    9
    Views:
    605
    Divyang M
    May 18, 2005
  3. hari_krishna

    FSM State transition coverage

    hari_krishna, Aug 22, 2006, in forum: VHDL
    Replies:
    0
    Views:
    923
    hari_krishna
    Aug 22, 2006
  4. Robert Winsor

    Sub-bit transition state?

    Robert Winsor, Oct 28, 2006, in forum: VHDL
    Replies:
    1
    Views:
    461
    Robert Winsor
    Oct 28, 2006
  5. Steven Kauffmann
    Replies:
    2
    Views:
    483
    Steven Kauffmann
    Dec 20, 2007
Loading...

Share This Page