Stefan
0) I've interleaved responses to your specific points below.
1) A sketch of an FSM with a Request input, a Strobe output and an Ack input
follows [E&OE]
No testbench, no syntax check, no testing and no warranty.
Note that, as the clock is continuous, I've used synchronous resets; you
always should when you can.
State encoding, timeout, illegal state recovery and post synthesis V&V
are left as exercises for the reader.
Hope this is of assistance
Martin
entity FSM
is port (Rst_n : in Std_Logic;
Clk : in Std_Logic;
Request : in Std_Logic; -- usually this would be negative
active
Strobe : out Std_Logic;
Ack : in Std_Logic);
end FSM;
architecture Synthesisable of FSM
is
type tFSM is (FsmIdle, FsmAssert, FsmArmed);
signal srFSM : tFSM;
signal Rst_n_d1,
Rst_n_d2,
Request_d1,
Request_d2,
Request_d3,
Ack_d1,
Ack_d2 : Std_Logic;
begin
pSynchReset:
process
if Reset_n = '0'
then Rst_n_d1 <= '0';
Rst_n_d2 <= '0';
elsif rising_edge (Clk)
then Rst_n_d1 <= Rst_n;
Rst_n_d2 <= Rst_n_d1;
end if;
end process pSynchReset;
pSynchRequest:
process
wait for rising_edge (Clk);
Request_d1 <= Request;
Request_d2 <= Request_d1;
Request_d3 <= Request_d2;
end if;
end process pSynchRequest;
pSynchAck:
process
wait for rising_edge (Clk);
Ack_d1 <= Ack;
Ack_d2 <= Ack_d1;
end if;
end process pSynchAck;
pFSM:
process
var vFSM : tFSM;
begin
wait for rising_edge(Clk);
vFSM := srFSM;
if Rst_n_d2 = '0'
then vFSM := FsmIdle;
else case srFSM is
when FsmIdle
=> if (Request_d1 xor Request_d2) = '1' -- Request line
toggles to initiate FSM
then vFSM := FsmAssert;
end if;
when FsmAssert
=> if (Ack_d2 = '1') and (Ack_d3 = '0') -- wait for
rising edge on Ack
then vFSM := FsmArmed;
end if;
when FsmArmed
=> if Ack_d3 = '1' -- wait for two 'samples' of Ack
(intentionally clumsy)
then vFSM := FsmIdle;
end if;
when others
=> assert ...
end case srFSM;
end if;
srFSM <= vFSM; -- location imaterial, as long as it's after the wait
case vFSM is -- vFSM to update State and Strobe simulatneously
when FsmIdle
=> Strobe <= '0';
when FsmAssert,
FsmArmed
=> Strobe <= '1';
when others
=> assert ...
end case;
end process; -- pFSM
end Synthesisable; -- of FSM
Stefan Oedenkoven said:
Hi Martin & Pieter,
thanks for your comments...
so variables are simply synthesized to latches? if not - when do i use
variables or should i avoid them generally?
Yes, variables which implement sequential logic (requiring memory) inside
proceses will be synthesised as latches or flip flops; usually you don't
want to synthesise latches, and the implicit synthesis of flip flops leaves
details such as reset (perhaps) indeterminate.
A good use for variables, IMHO, is for intermediate combinatorial results;
e.g. next state
so, then i need only one signal for the state assignment...
Not certain what you mean. But, the vX_read logic would be subsumed into
the FSM
registers? hmmm it's optional for the signal declaration, right? but i
didn't find anything about this in my vhdl book. Will register-signals
always synthesized to flip-flops? where is the difference to a 'normal'
signal?
Register = flip flop (in this usage); the rationale for output registers is
that the outputs occur after Tclock-to-output rather than Tdata-to-output.
Or, in Mealy / Moore argot: use a Moore machine [see e.g. Cohen, ISBN
0-7923-8474-1 p299]
why is it not sufficient to use two FFs and wait for FF_1 = '1' and FF_2 =
'0'
Metastability will (eventually) bite if you don't use a 'synchroniser',
hence the 'extra' FF; use Google to find references e.g. from the silicon
vendors and FAQs
require
erm, what did you mean?
What I mean is are you looking for the 0/1 transition or for 0/1/1, as
sugested by your initial posting
FSM
ok, my literature say's for CPLD is binary and for FPGA is 1-hot is
appropriate.
Hmm, those are the default but not necessarily apropriate encodings. If
your design is more than an example, you should read up on this.
ok if i programm a CPLD / FPGA and don't be aware of the exact timings i
should alway avoid asynchronous inputs to FSMs - did i catch this right?
Absolutely, synchronise everything that enters clocked logic including
reset. Or, you're playing hardball.