std.textio and ieee.std_logic_textio procedure overloading

Discussion in 'VHDL' started by Magne Munkejord, Aug 23, 2006.

  1. Hi,

    I have problems using both std.textio.all and ieee.std_logic_textio.all
    When I try to compile ModelSim gives me an error: Subprogram 'write' is
    ambiguous. Suitable definitions exist in packages 'std_logic_textio' and
    'textio'.

    When i take a look at source code for std_logic_textio it says:
    -- Purpose: This package overloads the standard TEXTIO procedures
    -- READ and WRITE.

    This is exactly what I want it to do. Any tips how to make this happen?
     
    Magne Munkejord, Aug 23, 2006
    #1
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  2. Magne Munkejord wrote:
    > Hi,
    >
    > I have problems using both std.textio.all and ieee.std_logic_textio.all
    > When I try to compile ModelSim gives me an error: Subprogram 'write' is
    > ambiguous. Suitable definitions exist in packages 'std_logic_textio' and
    > 'textio'.
    >
    > When i take a look at source code for std_logic_textio it says:
    > -- Purpose: This package overloads the standard TEXTIO procedures
    > -- READ and WRITE.
    >
    > This is exactly what I want it to do. Any tips how to make this happen?


    I found a solution:
    write(my_line, string'("my_string");
    instead of:
    write(my_line, "my_string");

    (my_line is type LINE as defined in std.textio)
     
    Magne Munkejord, Aug 23, 2006
    #2
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