std types

Discussion in 'VHDL' started by Nipo, Oct 23, 2010.

  1. Nipo

    Nipo Guest

    Hi,
    i am new in VHDL and i not understand what advantage in use types
    std_logic/std_ulogic and std_logic_vector/std_ulogic_vector? I always
    use types bit and bit_vector, but i always see in examples the use of
    these types.
    Thanks.
     
    Nipo, Oct 23, 2010
    #1
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  2. Nipo

    KJ Guest

    On Oct 23, 6:16 pm, Nipo <> wrote:
    > Hi,
    > i am new in VHDL and i not understand what advantage in use types
    > std_logic/std_ulogic and std_logic_vector/std_ulogic_vector? I always
    > use types bit and bit_vector, but i always see in examples the use of
    > these types.
    > Thanks.


    std_logic and std_ulogic bring along the concepts of unknown values,
    strong and weak driving as well as high impedance. Whereas a 'bit'
    can only be '0' or '1', a std_logic/std_ulogic has the following
    definition
    TYPE std_ulogic IS ( 'U', -- Uninitialized
    'X', -- Forcing Unknown
    '0', -- Forcing 0
    '1', -- Forcing 1
    'Z', -- High Impedance
    'W', -- Weak Unknown
    'L', -- Weak 0
    'H', -- Weak 1
    '-' -- Don't care

    The 'weak' values 'W', 'L' and 'H' somewhat model the way a resistor
    on a board behaves. While you can't tie two outputs together and not
    expect conflicts, you can tie them together through a resistor. The
    resolution rule if there is more than one driver for a signal is that
    'forcing' beats 'weak', so a '1' or '0' would trump a 'L' or an 'H'.
    Search the source file that contains the ieee std_logic_1164 package
    for the function called 'resolved' and you'll find the code that does
    it, which then defines the entire set of 81 rules for when these 9
    values crash together.

    'Z' is used to model tri-state outputs.

    'X' results when you have two drivers for a signal and they are going
    in different directions. So a '0' driver combined with a '1' driver
    cause the signal to be 'X'.

    'U' models the reality that not all signals power up with a known
    value. Sometimes it may power up as a '0', other times as a '1'.
    What 'U' does is say that the value is unknown.

    While most people generally think of digital systems in terms of '0'
    and '1' (i.e. type 'bit'), it is generally quite helpful to use
    std_logic/std_ulogic instead because a design that really does get
    everything initialized properly will have a designed in mechanism to
    change any 'U' into a known value. If you use 'bit' instead, you
    might find yourself in the situation where the simulation appears to
    be working, but that is because it is using a default value of '0' for
    a signal, and that '0' might not be something that happens in the
    normal course of events. In other words, you think everything is
    fine, but it's not...or at least it's not guaranteed to be working the
    way you expect. There are a few downsides to std_logic/std_ulogic,
    but for the most part the benefits outweigh the drawbacks.

    Kevin
     
    KJ, Oct 24, 2010
    #2
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  3. Nipo

    Andy Guest

    VHDL std_logic includes all of these features to ensure applicability
    and portability across test benches and a wide range of digital logic
    hardware, including board level, ASIC and FPGA.

    If your design targets only an FPGA that has a built-in initialization
    feature (such as most sram based ones have), and you are not
    specifying tri-state, wired-OR or wired-AND based logic or external
    interfaces, then you can use bit, bit_vector, and the related package
    numeric_bit, which defines unsigned and signed bit vectors, and
    arithmetic operators on them. Note that you can still specify
    explicit reset behavior, but if you are relying upon it, there is not
    a good way to verify it is done everywhere it is necessary, since bit
    does not have an "invalid' value to which to initialize. Using bit/
    bit_vector is not very common anymore, but it is done. Note that gate
    level post-synthesis or post-place&route models will generally have
    std_logic_vector based IO, regardless of what types you had for your
    IO in your RTL. That means you would have to create a wrapper for the
    device level entity, and in that convert back to bit/bit_vector for
    your testbench, assuming your testbench was written to work with your
    RTL.

    Under the same caveats, you can also use integer and its subtypes, but
    you are practically limited to maximum 32 bit signed and 31 bit
    unsigned quantities. Within these constraints, integer has several
    advantages, especially in simulation performance, over bit and
    std_logic based vectors.

    Andy
     
    Andy, Oct 25, 2010
    #3
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