Std_Logic signal assignment snafu

Discussion in 'VHDL' started by Norair, May 16, 2006.

  1. Norair

    Norair

    Joined:
    May 16, 2006
    Messages:
    2
    Location:
    Melbourne, FL
    As you can tell, I'm new to VHDL. I have tried searching this forum, but the search tool either doesn't work or I have come up short.

    I am using the downloadable Xilinx ISE. I have this line of code, for example:

    RXSize(3 downto 0) <= B"0001";

    RXSize is a 4bit long std_logic_vector SIGNAL. I know that I must be doing something wrong with the types, but I can't for the life of me figure it out since the same nomenclature (i.e. B"XXXX") seems to work declaring for the initial values.

    This is irritating, because I have a fair amount of logic design experience and would like to get on with the project!
     
    Norair, May 16, 2006
    #1
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