std_logic_vector clock delay format

[Brad Smallridge]

What is the best way to write a
series of delayed std_logic_vectors
to replace the verbose code below:

if(clk'event and clk='1')then
data_1 <= data_in;
data_2 <= data_1;
data_3 <= data_2;
etc.

Thanks,
Brad Smallridge
aivision

 

[Mike Treseler]

What is the best way to write a
series of delayed std_logic_vectors
to replace the verbose code below:

if(clk'event and clk='1')then
data_1 <= data_in;
data_2 <= data_1;
data_3 <= data_2;
etc.

It may not be best, or less verbose,
but I would declare a register array like this:

subtype reg_t is std_logic_vector(reg_len_c-1 downto 0);
type regs_t is array (0 to array_len_c-1) of reg_t;
variable regs_v : regs_t;

And update it something like this:

regs_v := d & regs_v(0 to array_len_c-2); -- push D into r0

see register stack source here for a related example:
http://mysite.verizon.net/miketreseler/

Good luck.

-- Mike Treseler

 

[Mike Treseler]

As Mike said, you could make an array for your
numerous delay stages. Alternatively, if this is
a requirement you meet often, you could consider
packaging the whole mess as a block or even as an
entity. It could be a procedure too, but the form
of procedure you would need is unlikely to be
synthesisable.

I would agree that a packaged procedure
is not worth the overhead in this case.
If the array dimensions are
constrained by a package or generic,
then the update procedure is a one-liner.

Here's the entity flavour:

Nice example using unconstrained ports.

I don't know whether this helps with your real needs,
and you need to check my code for typos because I
haven't tested it.

Your code worked for me.

-- Mike Treseler

 

[no_spa2005]

Hi,

Please note that unconstrained ports are not (currently) supported by
Xilinx tools (ISE/Xst 10.1.03).

Best regards.

 

[no_spa2005]

Hi Jonathan,

Thanks ! you're right, it works with length attribute. With range
attribute, you have :
FATAL_ERROR:Xstortability/export/Port_Main.h:143:1.17 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. For technical support on this
issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.

Very helpful message !
In Xilinx documentation (xst.pdf, p494), about XST VHDL Language
Support, it's written : Ports : Supported (no unconstrained ports).
May be you can check in 8.2 documentation if it's the same. So it's
not "officially" supported. May be if we are several to open a Webcase
they will perhaps correct this bug ? (...)
Regards.