std_logic_vector entry as hexadecimal : Different behaviors

[Sylvain Munaut]

Hello,


To ease the entry of 32 bits constants, I'd like to be have things like :


signal test : std_logic_vector(31 downto 0);

test <= x"01234567";


And that works fine in XSE & Symplify.

But when I simulate on ModelSim, that doesn't work, I'm forced to used the
heavier

test <= to_stdlogicvector(x"01234567");


But that doesn't work in XSE ! It says that to_stdlogicvector can mean
two things in this context.


Is there a way to make ModelSim understand the first notation ?



Sylvain

 

[Paul Uiterlinden]

Hello,


To ease the entry of 32 bits constants, I'd like to be have things like :


signal test : std_logic_vector(31 downto 0);

test <= x"01234567";


And that works fine in XSE & Symplify.

But when I simulate on ModelSim, that doesn't work, I'm forced to used the
heavier
test <= to_stdlogicvector(x"01234567");

That's because you're using 1076-1987 mode. Use 1993 or 2002 instead
(vcom -93 switch or -2002 switch, or in modelsim.ini).

But that doesn't work in XSE ! It says that to_stdlogicvector can mean
two things in this context.

That's because you're using 1076-1993 or 2002 here. Since the 1993
standard bit_vectors (x"01234567") may also be used as std_logic_vector,
so your expression is now ambiguous.

Is there a way to make ModelSim understand the first notation ?

As said above, -93 or -2002 switch of vcom.

Paul.

 

[Sylvain Munaut]

Hello

That's because you're using 1076-1987 mode. Use 1993 or 2002 instead
(vcom -93 switch or -2002 switch, or in modelsim.ini).

Thanks, the -93 works fine.
( -2002 doesn't exist in my version of modelsim )

Sylvain