Uvbaz,
For "=" and "/=" there is no reason not to
use std_logic_vector directly in the comparision.
Hence, your code becomes:
if( op(3 downto 1) = "110" ) then
For using ">", ">", ">=", and "<=", it is easiest to
use a type conversion to convert to unsigned
(as Andy suggested). Also make sure to use the
package "numeric_std". So if you were doing ">",
use ieee.numeric_std.all ; -- before the entity
....
if( unsigned(op(3 downto 1)) > "110" ) then
Due to overloading in numeric_std, it is also valid
to use integer literals with unsigned, and hence the
following are also valid:
if( unsigned(op(3 downto 1)) > 6 ) then
if( unsigned(op(3 downto 1)) > 2#110# ) then
Note that 2#110# is an integer literal (use where integers
can be used), whereas, "110" is a string literal, which
can be use with any array type based on character types
(such as unsigned, std_logic_vector, ...). A few character
based types are character, bit, std_ulogic and std_logic.
Cheers,
Jim
P.S.
Ironically in VHDL understanding types and values is one
of the hard things. However, once you get past beginner
mistakes, these will start to work in your favor - ie: find
bugs at compile time that would otherwise take simulation
and a good testbench to find.
--
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Jim Lewis
Director of Training mailto:
[email protected]
SynthWorks Design Inc.
http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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