std_logic_vector on a single pin

Discussion in 'VHDL' started by unlikeablePorpoise@gmail.com, Jul 9, 2006.

  1. Guest

    Is it possible to cause std_logic_vector inputs to be assigned to a
    single pin? I have a 308 bit word as input and the synthesizer always
    assumes that this will be on separate pins. This exceeds the pin count
    on the FPGA and I am unable to run timing simulations. Does anybody
    know of a way around this?

    Thanks,

    James
     
    , Jul 9, 2006
    #1
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  2. a écrit :
    > Is it possible to cause std_logic_vector inputs to be assigned to a
    > single pin? I have a 308 bit word as input and the synthesizer always
    > assumes that this will be on separate pins. This exceeds the pin count
    > on the FPGA and I am unable to run timing simulations. Does anybody
    > know of a way around this?
    >
    > Thanks,
    >
    > James


    Hello James,

    How this 308 bit data will be inputed into your device ? Not in parallel
    way of course ! So, why do you wants to implement it as parallel input ?

    Implement its input (ie serial or successive 32 bit loading) and you
    will be able to simulate both its loading and uses.

    If you wants to simulate only its usage, implement it as internal signal
    and use reset to load a predefined value.

    Pascal
     
    Pascal Peyremorte, Jul 9, 2006
    #2
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